| High-level language tools for reconfigurable computing S Windh, X Ma, RJ Halstead, P Budhkar, Z Luna, O Hussaini, WA Najjar Proceedings of the IEEE 103 (3), 390-408, 2015 | 95 | 2015 |
| An open-source compiler and PCB synthesis tool for digital microfluidic biochips D Grissom, C Curtis, S Windh, C Phung, N Kumar, Z Zimmerman, ... INTEGRATION, the VLSI journal 51, 169-193, 2015 | 68 | 2015 |
| Performance improvements and congestion reduction for routing-based synthesis for digital microfluidic biochips S Windh, C Phung, DT Grissom, P Pop, P Brisk IEEE transactions on computer-aided design of integrated circuits and …, 2016 | 24 | 2016 |
| FPGA-accelerated group-by aggregation using synchronizing caches I Absalyamov, P Budhkar, S Windh, RJ Halstead, WA Najjar, VJ Tsotras Proceedings of the 12th International Workshop on Data Management on New …, 2016 | 22 | 2016 |
| CAMs as synchronizing caches for multithreaded irregular applications on FPGAs S Windh, P Budhkar, WA Najjar 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 331-336, 2015 | 8 | 2015 |
| Accelerating in-memory database selections using latency masking hardware threads P Budhkar, I Absalyamov, V Zois, S Windh, WA Najjar, VJ Tsotras ACM Transactions on Architecture and Code Optimization (TACO) 16 (2), 1-28, 2019 | 6 | 2019 |
| Reinforcement Learning Approach for Mapping Applications to Dataflow-Based Coarse-Grained Reconfigurable Array AXM Chang, P Khopkar, B Romanous, A Chaurasia, P Estep, S Windh, ... arXiv preprint arXiv:2205.13675, 2022 | 2 | 2022 |
| Masking for coarse grained reconfigurable architecture B Hornung, SA Windh US Patent App. 17/402,997, 2023 | 1 | 2023 |
| Debugging dataflow computer architectures SA Windh, TM Brewer, P Estep US Patent 11,507,493, 2022 | 1 | 2022 |
| Efficient local locking for massively multithreaded in-memory hash-based operators B Romanous, S Windh, I Absalyamov, P Budhkar, R Halstead, W Najjar, ... The VLDB Journal 30 (3), 333-359, 2021 | 1 | 2021 |
| Hashing, Caching, and Synchronization: Memory Techniques for Latency Masking Multithreaded Applications SA Windh University of California, Riverside, 2018 | 1 | 2018 |
| Debugging dataflow computer architectures SA Windh, TM Brewer, P Estep US Patent 11,720,475, 2023 | | 2023 |
| Saturating local cache in memory-compute systems SA Windh, R Meyer US Patent 11,698,853, 2023 | | 2023 |
| Packing conditional branch operations SA Windh, G Wang US Patent App. 18/120,532, 2023 | | 2023 |
| Packing conditional branch operations SA Windh, G Wang US Patent 11,604,650, 2023 | | 2023 |
| Mechanism to trigger early termination of cooperating processes P Estep, SA Windh, TM Brewer US Patent App. 17/984,817, 2023 | | 2023 |
| Parallel matrix operations in a reconfigurable compute fabric SA Windh, D Vanesko US Patent App. 17/392,756, 2023 | | 2023 |
| Managing return parameter allocation T Brewer, P Estep, SA Windh US Patent App. 17/405,646, 2023 | | 2023 |
| Mechanism to trigger early termination of cooperating processes P Estep, SA Windh, TM Brewer US Patent 11,550,642, 2023 | | 2023 |
| Dynamic decomposition and thread allocation SA Windh, TM Brewer, P Estep US Patent App. 17/465,021, 2022 | | 2022 |
Walid NajjarUniversity of California RiversideGeverifieerd e-mailadres voor cs.ucr.edu
