Seung Hoon Sung
Seung Hoon Sung
Senior research staff of Components Research, Intel Corporation
Verified email at
Cited by
Cited by
Transistor source/drain amorphous interlayer arrangements
A Agrawal, B Chu-Kung, SH Sung, S Chouksey, GA Glass, VH Le, ...
US Patent App. 16/347,110, 2019
300mm heterogeneous 3D integration of record performance layer transfer germanium PMOS with silicon NMOS for low power high performance logic applications
W Rachmady, A Agrawal, SH Sung, G Dewey, S Chouksey, B Chu-Kung, ...
2019 IEEE International Electron Devices Meeting (IEDM), 29.7. 1-29.7. 4, 2019
Variable gate width for gate all-around transistors
W Rachmady, VH Le, R Pillarisetty, JT Kavalieros, RS Chau, SH Sung
US Patent 9,590,089, 2017
Trench confined epitaxially grown device layer (s)
R Pillarisetty, SH Sung, N Goel, JT Kavalieros, S Dasgupta, VH Le, ...
US Patent 8,765,563, 2014
Time-frequency domain reflectometry apparatus and method
JB Park, YJ Shin, J Yook, EJ Powers, ES Song, JW Kim, TS Choe, ...
US Patent 7,337,079, 2008
Plasma science and technology in the limit of the small: Microcavity plasmas and emerging applications
JG Eden, SJ Park, JH Cho, MH Kim, TJ Houlahan, B Li, ES Kim, TL Kim, ...
IEEE Transactions on Plasma Science 41 (4), 661-675, 2013
Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al0.83In0.17N/AlN/GaN MOS-HEMT on …
HW Then, S Dasgupta, M Radosavljevic, L Chow, B Chu-Kung, G Dewey, ...
2013 IEEE International Electron Devices Meeting, 28.3. 1-28.3. 4, 2013
Nonplanar III-N transistors with compositionally graded semiconductor channels
HW Then, S Dasgupta, M Radosavljevic, B Chu-Kung, SH Sung, ...
US Patent 8,896,101, 2014
III-N devices in Si trenches
S Dasgupta, HW Then, SK Gardner, SH Sung, M Radosavljevic, ...
US Patent 9,640,422, 2017
Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack
S Dasgupta, HW Then, M Radosavljevic, SK Gardner, SH Sung, ...
US Patent 9,660,064, 2017
Group III-N transistors on nanoscale template structures
HW Then, S Dasgupta, M Radosavljevic, B Chu-Kung, SK Gardner, ...
US Patent 8,768,271, 2014
Application of cross time-frequency analysis to postural sway behavior: the effects of aging and visual systems
YJ Shin, D Gobert, SH Sung, EJ Powers, JB Park
IEEE Transactions on Biomedical Engineering 52 (5), 859-868, 2005
Interchannel optical coupling within arrays of linear microplasmas generated in 25–200μm wide glass channels
SH Sung, IC Hwang, SJ Park, JG Eden
Applied Physics Letters 97 (23), 2010
Resistance and electromigration performance of 6 nm wires
JS Chawla, SH Sung, SA Bojarski, CT Carver, M Chandhok, RV Chebiam, ...
2016 IEEE International Interconnect Technology Conference/Advanced …, 2016
High-performance low-leakage enhancement-mode high-K dielectric GaN MOSHEMTs for energy-efficient, compact voltage regulators and RF power amplifiers for low-power mobile SoCs
HW Then, LA Chow, S Dasgupta, S Gardner, M Radosavljevic, VR Rao, ...
2015 Symposium on VLSI Technology (VLSI Technology), T202-T203, 2015
Nanowire transistor fabrication with hardmask layers
SH Sung, S Kim, K Kuhn, W Rachmady, J Kavalieros
US Patent 10,121,861, 2018
FeRAM using anti-ferroelectric capacitors for high-speed and high-density embedded memory
SC Chang, N Haratipour, S Shivaraman, C Neumann, S Atanasov, J Peck, ...
2021 IEEE International Electron Devices Meeting (IEDM), 33.2. 1-33.2. 4, 2021
Nickel silicide for interconnects
KL Lin, SA Bojarski, CT Carver, M Chandhok, JS Chawla, JS Clarke, ...
2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015
Nonplanar III-N transistors with compositionally graded semiconductor channels
HW Then, S Dasgupta, M Radosavljevic, B Chu-Kung, SH Sung, ...
US Patent 9,806,203, 2017
Deep gate-all-around semiconductor device having germanium or group III-V active layer
R Pillarisetty, W Rachmady, VH Le, SH Sung, JS Kachian, JT Kavalieros, ...
US Patent 9,136,343, 2015
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