| Analytical Fault Tolerance Assessment and Metrics for TSV-based 3D Network-on-Chip A Eghbal, P M Yaghini, N Bagherzadeh, M Khayambashi Computers, IEEE Transactions on, 2015 | 71 | 2015 |
| Designing fault-tolerant network-on-chip router architecture A Eghbal, PM Yaghini, H Pedram, HR Zarandi International Journal of Electronics 97 (10), 1181-1192, 2010 | 26 | 2010 |
| Investigation of transient fault effects in synchronous and asynchronous Network on Chip router PM Yaghini, A Eghbal, H Pedram, HR Zarandi Journal of Systems Architecture 57 (1), 61-68, 2011 | 23 | 2011 |
| Investigation of transient fault effects in an asynchronous NoC router PM Yaghini, A Eghbal, H Pedram, HR Zarandi 2010 18th Euromicro Conference on Parallel, Distributed and Network-based …, 2010 | 21 | 2010 |
| Analytical reliability analysis of 3D NoC under TSV failure M Khayambashi, PM Yaghini, A Eghbal, N Bagherzadeh ACM Journal on Emerging Technologies in Computing Systems (JETC) 11 (4), 1-16, 2015 | 20 | 2015 |
| Three-dimensional NoC reliability evaluation A Eghbal, PM Yaghini, N Bagherzadeh US Patent 11,093,673, 2021 | 19 | 2021 |
| Capacitive and inductive tsv-to-tsv resilient approaches for 3d ics PM Yaghini, A Eghbal, SS Yazdi, N Bagherzadeh, MM Green IEEE Transactions on Computers 65 (3), 693-705, 2015 | 18 | 2015 |
| Power comparison of an asynchronous and synchronous network on chip router PM Yaghini, A Eghbal, SA Asghari, H Pedram 2009 14th International CSI Computer Conference, 242-246, 2009 | 17 | 2009 |
| Fault injection-based evaluation of a synchronous noc router A Eghbal, PM Yaghini, H Pedram, HR Zarandi 2009 15th IEEE International On-Line Testing Symposium, 212-214, 2009 | 16 | 2009 |
| Deadlock verification of cache coherence protocols and communication fabrics F Verbeek, PM Yaghini, A Eghbal, N Bagherzadeh IEEE Transactions on Computers 66 (2), 272-284, 2016 | 13 | 2016 |
| Tsv-to-tsv inductive coupling-aware coding scheme for 3d network-on-chip A Eghbal, PM Yaghini, SS Yazdi, N Bagherzadeh 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2014 | 13 | 2014 |
| On the design of hybrid routing mechanism for mesh-based network-on-chip PM Yaghini, A Eghbal, N Bagherzadeh Integration 50, 183-192, 2015 | 12 | 2015 |
| A gals router for asynchronous network-on-chip PM Yaghini, A Eghbal, N Bagherzadeh Proceedings of International Workshop on Manycore Embedded Systems, 52-55, 2014 | 9 | 2014 |
| Capacitive Coupling Mitigation for TSV-based 3D ICs A Eghbal, PM Yaghini, N Bagherzadeh VLSI Test Symposium (VTS), 2015 IEEE 33rd, 1-6, 2015 | 8 | 2015 |
| Coupling mitigation in 3-D multiple-stacked devices PM Yaghini, A Eghbal, M Khayambashi, N Bagherzadeh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015 | 8 | 2015 |
| Fault tolerance assessment of pic microcontroller based on fault injection A Eghbal, HR Zarandi, PM Yaghini 2009 10th Latin American Test Workshop, 1-6, 2009 | 8 | 2009 |
| ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects F Verbeek, PM Yaghini, A Eghbal, N Bagherzadeh 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 7 | 2016 |
| Accurate system-level TSV-to-TSV capacitive coupling fault model for 3D-NoC PM Yaghini, A Eghbal, SS Yazdi, N Bagherzadeh Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015 | 7 | 2015 |
| An investigation of fault tolerance behavior of 32-bit dlx processor PM Yaghini, HR Zarandi, A Eghbal, A Jafarzadeh, S Eskandari 2009 Second International Conference on Dependability, 93-98, 2009 | 5 | 2009 |
| A compositional approach for verifying protocols running on on-chip networks F Verbeek, PM Yaghini, A Eghbal, N Bagherzadeh IEEE Transactions on Computers 67 (7), 905-919, 2017 | 1 | 2017 |
Pooria M. YaghiniPhD, University of California, IrvineVerified email at uci.edu
