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Behnam Amelifard
Behnam Amelifard
Director of Engineering, Qualcomm Inc
Verified email at qti.qualcomm.com - Homepage
Title
Cited by
Cited by
Year
Leakage Minimization of SRAM Cells in a Dual- and Dual- Technology
B Amelifard, F Fallah, M Pedram
IEEE transactions on very large scale integration (VLSI) systems 16 (7), 851-860, 2008
952008
NBTI-aware flip-flop characterization and design
H Abrishami, S Hatami, B Amelifard, M Pedram
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 29-34, 2008
942008
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment
B Amelifard, F Fallah, M Pedram
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
672006
Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders
B Amelifard, F Fallah, M Pedram
Sixth international symposium on quality electronic design (isqed'05), 148-152, 2005
632005
Optimal design of the power-delivery network for multiple voltage-island system-on-chips
B Amelifard, M Pedram
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
572009
Analog/mixed-signal design challenges in 7-nm CMOS and beyond
ALS Loke, D Yang, TT Wee, JL Holland, P Isakanian, K Rim, S Yang, ...
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018
442018
Improved multi-band spectral subtraction method for speech enhancement
Y Ghanbari, M Karami, B Amelifard
Proc. 6th IASTED internat. conf. on signal image process, 225-230, 2004
362004
Low-leakage SRAM design with dual V/sub t/transistors
B Amelifard, F Fallah, M Pedram
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-734, 2006
352006
A current source model for CMOS logic cells considering multiple input switching and stack effect
B Amelifard, S Hatami, H Fatemi, M Pedram
Proceedings of the conference on Design, automation and test in Europe, 568-573, 2008
342008
Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
F Fallah, B Amelifard, M Pedram
US Patent 7,573,775, 2009
242009
Design of an efficient power delivery network in an SoC to enable dynamic power management
B Amelifard, M Pedram
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
222007
Optimal selection of voltage regulator modules in a power delivery network
B Amelifard, M Pedram
Proceedings of the 44th annual Design Automation Conference, 168-173, 2007
202007
Low-power fanout optimization using multiple threshold voltage inverters
B Amelifard, F Fallah, M Pedram
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
202005
Dual mode clock/data recovery circuit
J Zhuang, NV Dang, X Kong, Z Zhu, T Sowlati, B Amelifard
US Patent 8,839,020, 2014
172014
Low-power fanout optimization using MTCMOS and multi-Vt techniques
B Amelifard, F Fallah, M Pedarm
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
152006
Adaptive output swing driver
M Li, B Amelifard, X Kong, NV Dang
US Patent App. 13/294,482, 2013
142013
Enhancing the efficiency of cluster voltage scaling technique for low-power application
B Amelifard, A Afzali-Kusha, A Khadernzadeh
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 1666-1669, 2005
132005
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
M Ghasemazar, B Amelifard, M Pedram
Proceedings of the 2008 international symposium on Low Power Electronics …, 2008
122008
PG-gated data retention technique for reducing leakage in memory cells
F Fallah, B Amelifard, M Pedram
US Patent 7,447,101, 2008
112008
Apparatuses, methods, and systems for glitch-free clock switching
CE Winemiller, B Amelifard, KL Arcudia, JR Boyette, CH Chang, ...
US Patent 9,509,318, 2016
102016
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