Chita R. Das
Geciteerd door
Geciteerd door
Towards characterizing cloud backend workloads: insights from google compute clusters
AK Mishra, JL Hellerstein, W Cirne, CR Das
ACM SIGMETRICS Performance Evaluation Review 37 (4), 34-41, 2010
ViChaR: A dynamic virtual channel regulator for network-on-chip routers
CA Nicopoulos, D Park, J Kim, N Vijaykrishnan, MS Yousif, CR Das
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ...
Proceedings of the 34th annual international symposium on Computer …, 2007
A low latency router supporting adaptivity for on-chip interconnects
J Kim, D Park, T Theocharides, N Vijaykrishnan, CR Das
Proceedings. 42nd Design Automation Conference, 2005., 559-564, 2005
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
A Jog, O Kayiran, N Chidambaram Nachiappan, AK Mishra, MT Kandemir, ...
ACM SIGPLAN Notices 48 (4), 395-406, 2013
Exploring fault-tolerant network-on-chip architectures
D Park, C Nicopoulos, J Kim, N Vijaykrishnan, CR Das
International Conference on Dependable Systems and Networks (DSN'06), 93-104, 2006
MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
2008 International Symposium on Computer Architecture, 251-261, 2008
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das
DAC Design Automation Conference 2012, 243-252, 2012
A gracefully degrading and energy-efficient modular router architecture for on-chip networks
J Kim, C Nicopoulos, D Park, V Narayanan, MS Yousif, CR Das
ACM SIGARCH Computer Architecture News 34 (2), 4-15, 2006
Cooperative cache-based data access in ad hoc networks
G Cao, L Yin, CR Das
Computer 37 (2), 32-39, 2004
Neither more nor less: Optimizing thread-level parallelism for GPGPUs
O Kayıran, A Jog, MT Kandemir, CR Das
Proceedings of the 22nd international conference on Parallel architectures …, 2013
Aergia: Exploiting packet latency slack in on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
ACM SIGARCH computer architecture news 38 (3), 106-116, 2010
Application-aware prioritization mechanisms for on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
R Das, S Eachempati, AK Mishra, V Narayanan, CR Das
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
Modeling and synthesizing task placement constraints in Google compute clusters
B Sharma, V Chudnovsky, JL Hellerstein, R Rifaat, CR Das
Proceedings of the 2nd ACM Symposium on Cloud Computing, 1-14, 2011
MDCSim: A multi-tier data center simulation, platform
SH Lim, B Sharma, G Nam, EK Kim, CR Das
2009 IEEE International Conference on Cluster Computing and Workshops, 1-9, 2009
Orchestrated scheduling and prefetching for GPGPUs
A Jog, O Kayiran, AK Mishra, MT Kandemir, O Mutlu, R Iyer, CR Das
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Hypercube communication delay with wormhole routing
J Kim, CR Das
IEEE Transactions on Computers 43 (7), 806-814, 1994
Design and analysis of an NoC architecture from performance, reliability and energy perspective
J Kim, D Park, C Nicopoulos, N Vijaykrishnan, CR Das
2005 Symposium on Architectures for Networking and Communications Systems …, 2005
Managing GPU concurrency in heterogeneous architectures
O Kayiran, NC Nachiappan, A Jog, R Ausavarungnirun, MT Kandemir, ...
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 114-126, 2014
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