| Handbook of algorithms for physical design automation CJ Alpert, DP Mehta, SS Sapatnekar CRC press, 2008 | 253 | 2008 |
| A histone methylation network regulates transgenerational epigenetic memory in C. elegans EL Greer, SE Beese-Sims, E Brookes, R Spadafora, Y Zhu, SB Rothbart, ... Cell reports 7 (1), 113-126, 2014 | 124 | 2014 |
| Method of playing game and gaming games with an additional payout indicator W Adams US Patent App. 10/157,607, 2002 | 114 | 2002 |
| The ISPD-2011 routability-driven placement contest and benchmark suite N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy Proceedings of the 2011 international symposium on Physical design, 141-146, 2011 | 98 | 2011 |
| Fast algorithms for slew-constrained minimum cost buffering S Hu, CJ Alpert, J Hu, SK Karandikar, Z Li, W Shi, CN Sze IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 93 | 2007 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 78 | 2007 |
| GLARE: global and local wiring aware routability evaluation Y Wei, C Sze, N Viswanathan, Z Li, CJ Alpert, L Reddy, AD Huber, ... DAC Design Automation Conference 2012, 768-773, 2012 | 77 | 2012 |
| The DAC 2012 routability-driven placement contest and benchmark suite N Viswanathan, C Alpert, C Sze, Z Li, Y Wei DAC Design Automation Conference 2012, 774-782, 2012 | 74 | 2012 |
| ISPD 2010 high performance clock network synthesis contest: benchmark suite and results CN Sze Proceedings of the 19th international symposium on Physical design, 143-143, 2010 | 73 | 2010 |
| Specifying circuit level connectivity during circuit design synthesis MD Amundson, D Kucar, R Puri, CN Sze, MM Ziegler US Patent 8,839,162, 2014 | 58 | 2014 |
| Accurate estimation of global buffer delay within a floorplan CJ Alpert, J Hu, SS Sapatnekar, CN Sze IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 49 | 2006 |
| The ISPD global routing benchmark suite GJ Nam, C Sze, M Yildiz Proceedings of the 2008 international symposium on Physical design, 156-159, 2008 | 48 | 2008 |
| Navigating registers in placement for clock network minimization Y Lu, CN Sze, X Hong, Q Zhou, Y Cai, L Huang, J Hu Proceedings of the 42nd annual Design Automation Conference, 176-181, 2005 | 48 | 2005 |
| Hinge assembly capable of damping door movement YJ Wang US Patent 6,684,453, 2004 | 48 | 2004 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 44 | 2012 |
| Physical synthesis with clock-network optimization for large systems on chips D Papa, C Alpert, C Sze, Z Li, N Viswanathan, GJ Nam, I Markov IEEE Micro 31 (4), 51-62, 2011 | 44 | 2011 |
| Ispd2009 clock network synthesis contest CN Sze, P Restle, GJ Nam, C Alpert Proceedings of the 2009 international symposium on Physical design, 149-150, 2009 | 44 | 2009 |
| RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm DA Papa, T Luo, MD Moffitt, CN Sze, Z Li, GJ Nam, CJ Alpert, IL Markov IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 44 | 2008 |
| Path-based buffer insertion CN Sze, CJ Alpert, J Hu, W Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 39 | 2007 |
| Latch placement for high performance and low power circuits CJ Alpert, S Ramji, CN Sze, PG Villarrubia US Patent 7,549,137, 2009 | 38 | 2009 |
Chuck AlpertSenior Software Architect, Cadence Design SystemsVerified email at cadence.com
