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Engin Afacan
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Year
Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
E Afacan, N Lourenço, R Martins, G Dündar
Integration, 2021
742021
Artificial neural network assisted analog IC sizing tool
G İslamoğlu, TO Çakici, E Afacan, G Dündar
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
392019
Neuron fault tolerance in spiking neural networks
T Spyrou, SA El-Sayed, E Afacan, LA Camuñas-Mesa, ...
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 743-748, 2021
332021
Using polynomial regression and artificial neural networks for reusable analog IC sizing
N Lourenço, E Afacan, R Martins, F Passos, A Canelas, R Póvoa, N Horta, ...
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
312019
Spiking neuron hardware-level fault modeling
SA El-Sayed, T Spyrou, A Pavlidis, E Afacan, LA Camuñas-Mesa, ...
2020 IEEE 26th International Symposium on On-Line Testing and Robust System …, 2020
222020
A mixed domain sizing approach for RF circuit synthesis
E Afacan, G Dündar
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
222016
Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2014 5th European Workshop on CMOS Variability (VARI), 1-6, 2014
222014
Reliability analysis of a spiking neural network hardware accelerator
T Spyrou, SA El-Sayed, E Afacan, LA Camuñas-Mesa, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 370-375, 2022
212022
Analog design methodologies for reliability in nanoscale CMOS circuits
E Afacan, MB Yelten, G Dündar
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
202017
A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena
E Afacan, G Berkol, G Dündar, AE Pusane, F Başkaya
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
202015
A novel yield aware multi-objective analog circuit optimization tool
G Berkol, E Afacan, G Dündar, AE Pusane, F Başkaya
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2652-2655, 2015
202015
A two-step layout-in-the-loop design automation tool
G Berkol, A Unutulmaz, E Afacan, G Dündar, FV Fernandez, AE Pusane, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
192015
An FPGA-based multiple-output PWM pulse generator for ultrasonic cleaning machines
A Tangel, M Yakut, E Afacan, U Güvenç, H Şengül
2010 international conference on applied electronics, 1-4, 2010
182010
A hybrid quasi monte carlo method for yield aware analog circuit sizing tool
E Afacan, G Berkol, AE Pusane, G Dündar, F Başkaya
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
172015
Inversion coefficient optimization assisted analog circuit sizing tool
E Afacan, G Dündar
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
142017
A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization
E Afacan, G Dundar
Integration 67, 162-169, 2019
132019
An analog circuit synthesis tool based on efficient and reliable yield estimation
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Microelectronics Journal 54, 14-22, 2016
132016
Sensitivity based methodologies for process variation aware analog IC optimization
E Afacan, G Berkol, F Başkaya, G Dündar
2014 10th Conference on Ph. D. Research in Microelectronics and Electronics …, 2014
132014
A lifetime-aware analog circuit sizing tool
E Afacan, G Berkol, G Dundar, AE Pusane, F Baskaya
Integration 55, 349-356, 2016
122016
Reliability enhancement using in-field monitoring and recovery for RF circuits
D Chang, S Ozev, B Bakkaloglu, S Kiaei, E Afacan, G Dundar
2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014
122014
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