| A dual-channel Compass/GPS/GLONASS/Galileo reconfigurable GNSS receiver in 65 nm CMOS with on-chip I/Q calibration N Qi, Y Xu, B Chi, X Yu, X Zhang, N Xu, P Chiang, W Rhee, Z Wang Circuits and Systems I: Regular Papers, IEEE Transactions on 59 (8), 1720-1732, 2012 | 64 | 2012 |
| A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation N Xu, W Rhee, Z Wang Solid-State Circuits, IEEE Journal of 49 (10), 2172-2186, 2014 | 34 | 2014 |
| Low power, non invasive UWB systems for WBAN and biomedical applications W Rhee, N Xu, B Zhou, Z Wang Information and Communication Technology Convergence (ICTC), 2010 …, 2010 | 26 | 2010 |
| Fractional-N Frequency Synthesis W Rhee, N Xu, B Zhou, Z Wang Journal of Semiconductor Technology and science 13 (2), 170-183, 2013 | 21* | 2013 |
| A 1.75 mW 1.1 GHz semi-digital fractional-N PLL with TDC-less hybrid loop control Y Sun, Z Zhang, N Xu, M Wang, W Rhee, TY Oh, Z Wang Microwave and Wireless Components Letters, IEEE 22 (12), 654-656, 2012 | 18 | 2012 |
| A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order???? modulation N Xu, Y Shen, S Lv, W Rhee, Z Wang Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian, 1-4, 2015 | 14 | 2015 |
| A 2.74–5.37 GHz boosted-gain type-I PLL with &# 60; 15% loop filter area Y Sun, J Li, Z Zhang, M Wang, N Xu, H Lv, W Rhee, Y Li, Z Wang Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE, 181-184, 2012 | 12 | 2012 |
| All-digital PLL with ΔΣ DLL embedded TDC Y Han, D Lin, S Geng, N Xu, W Rhee, TY Oh, Z Wang Electronics Letters 49 (2), 93-94, 2013 | 11 | 2013 |
| A 0.65 V 1.2 mW 2.4 GHz/400MHz dual-mode phase modulator for mobile healthcare applications Y Li, N Xu, Y Zhang, W Rhee, S Kang, Z Wang Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian, 261-264, 2014 | 8 | 2014 |
| A 2 GHz 2 Mb/s Semi-Digital-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 m CMOS N Xu, W Rhee, Z Wang Microwave and Wireless Components Letters, IEEE 25 (4), 253-255, 2015 | 7 | 2015 |
| A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation S Geng, N Xu, J Li, X Yu, W Rhee, Z Wang Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 1179-1182, 2013 | 7 | 2013 |
| Semidigital PLL design for low-cost low-power clock generation N Xu, W Rhee, Z Wang Journal of Electrical and Computer Engineering 2011, 8, 2011 | 6 | 2011 |
| A 10 Mb/s hybrid two-point modulator with front-end phase selection and dual-path DCO modulation X Li, S Lv, X Liu, N Xu, W Rhee, W Jia, Z Wang Wireless Symposium (IWS), 2015 IEEE International, 1-4, 2015 | 5 | 2015 |
| A 6.5 mW, wide band dual-path LC VCO design with mode switching technique in 130nm CMOS J Li, N Xu, Y Sun, W Rhee, Z Wang Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2015 IEEE 15th …, 2015 | 5 | 2015 |
| An 11.7–17.2 GHz digitally-controlled oscillator in 65nm CMOS for high-band UWB applications D Lin, N Xu, W Rhee, Z Wang Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th …, 2012 | 4 | 2012 |
| A digital-intensive F/PLL-based two-point modulator with a constant-gain DCO for linear FMCW generation N Xu, S Lv, W Rhee, Z Wang Radio-Frequency Integration Technology (RFIT), 2015 IEEE International …, 2015 | 3 | 2015 |
| A 9.6 Gb/s 5+ 1-lane source synchronous transmitter in 65nm CMOS technology K Huang, C Jia, X Zheng, N Xu, C Zhang, W Rhee, Z Wang Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, 313-316, 2012 | 3 | 2012 |
| A 4.8-mW/Gb/s 9.6-Gb/s 5 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS S Yuan, Z Wang, X Zheng, K Huang, N Xu, W Rhee, L Wu, C Zhang Circuits and Systems II: Express Briefs, IEEE Transactions on 61 (4), 209-213, 2014 | 2 | 2014 |
| Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2–6GHz software-defined radio frequency synthesis J Li, N Xu, Y Sun, W Rhee, Z Wang Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on, 1135-1138, 2010 | 2 | 2010 |
| Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit Y Liu, N Xu, W Rhee, Z Wang, Z Wang Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on, 939-942, 2010 | 2 | 2010 |
