Anmol Mathur
Titel
Geciteerd door
Geciteerd door
Jaar
Rate analysis for embedded systems
A Mathur, A Dasdan, RK Gupta
ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (3 …, 1998
731998
Functional equivalence verification tools in high-level synthesis flows
A Mathur, M Fujita, E Clarke, P Urard
IEEE Design & Test of Computers 26 (4), 88-95, 2009
332009
Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs
A Mathur, CL Liu
Proceedings ED&TC European Design and Test Conference, 165-169, 1996
331996
Non-cycle-accurate sequential equivalence checking
P Chauhan, D Goyal, G Hasteer, A Mathur, N Sharma
2009 46th ACM/IEEE Design Automation Conference, 460-465, 2009
322009
Embedded tutorial: Formal equivalence checking between system-level models and RTL
A Koelbl, Y Lu, A Mathur
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
322005
Procedure for optimizing mergeability and datapath widths of data flow graphs
S Saluja, A Mathur
US Patent 6,807,651, 2004
302004
Circuit comparison by information loss matching
A Mathur, D Goyal
US Patent 7,222,317, 2007
272007
Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision
S Saluja, A Mathur
US Patent 6,772,399, 2004
222004
Improved merging of datapath operators using information content and required precision analysis
A Mathur, S Saluja
Proceedings of the 38th annual Design Automation Conference, 462-467, 2001
212001
Power reduction techniques and flows at RTL and system level
A Mathur, Q Wang
2009 22nd International Conference on VLSI Design, 28-29, 2009
172009
System, method and computer program product for equivalence checking between designs with sequential differences
A Mathur, N Sharma, D Goyal, G Hasteer, R Mukherjee
US Patent 7,350,168, 2008
152008
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems
A Dasdan, A Mathur, RK Gupta
Proceedings European Design and Test Conference. ED & TC 97, 2-6, 1997
151997
Re-engineering of timing constrained placements for regular architectures
A Mathur, KC Chen, CL Liu
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
141995
Compression-relaxation: A new approach to performance driven placement for regular architectures
A Mathur, CL Liu
IEEE/ACM International Conference on Computer-Aided Design, 130,131,132,133 …, 1994
131994
Design for Verification in System-level Models and RTL
A Mathur, V Krishnaswamy
2007 44th ACM/IEEE Design Automation Conference, 193-198, 2007
122007
Reducing datapath widths by rebalancing data flow topology
S Saluja, A Mathur
US Patent 6,832,357, 2004
12*2004
Efficient equivalence checking of multi-phase designs using retiming
G Hasteer, A Mathur, P Banerjee
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1998
121998
Performance driven technology mapping for lookup-table based FPGAs using the general delay model
A Mathur, CL Liu
International Workshop on Field Programmable Gate Arrays 326, 1994
111994
Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions
V Ramachandran, N Tripathi, A Mathur, S Roy, M Haldar
US Patent 7,761,827, 2010
102010
Reducing datapath widths responsively to upper bound on information content
S Saluja, A Mathur
US Patent 6,772,398, 2004
102004
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–20