Sujoy Sinha Roy
Sujoy Sinha Roy
Assistant Professor, IAIK, TU Graz
Geverifieerd e-mailadres voor iaik.tugraz.at - Homepage
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Compact ring-LWE cryptoprocessor
SS Roy, F Vercauteren, N Mentens, DD Chen, I Verbauwhede
International workshop on cryptographic hardware and embedded systems, 371-391, 2014
2462014
Saber: Module-LWR based key exchange, CPA-secure encryption and CCA-secure KEM
JP D’Anvers, A Karmakar, SS Roy, F Vercauteren
International Conference on Cryptology in Africa, 282-305, 2018
195*2018
Efficient software implementation of ring-LWE encryption
R De Clercq, SS Roy, F Vercauteren, I Verbauwhede
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 339-344, 2015
1222015
High-speed polynomial multiplication architecture for ring-LWE and SHE cryptosystems
DD Chen, N Mentens, F Vercauteren, SS Roy, RCC Cheung, D Pao, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 157-166, 2014
1132014
Efficient Ring-LWE encryption on 8-bit AVR processors
Z Liu, H Seo, SS Roy, J Großschädl, H Kim, I Verbauwhede
International Workshop on Cryptographic Hardware and Embedded Systems, 663-682, 2015
1022015
High precision discrete Gaussian sampling on FPGAs
SS Roy, F Vercauteren, I Verbauwhede
International Conference on Selected Areas in Cryptography, 383-401, 2013
862013
A masked ring-LWE implementation
O Reparaz, SS Roy, F Vercauteren, I Verbauwhede
International Workshop on Cryptographic Hardware and Embedded Systems, 683-702, 2015
852015
Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs
C Rebeiro, SS Roy, D Mukhopadhyay
International Workshop on Cryptographic Hardware and Embedded Systems, 494-511, 2012
732012
FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data
SS Roy, F Turan, K Jarvinen, F Vercauteren, I Verbauwhede
2019 IEEE International symposium on high performance computer architecture …, 2019
662019
Additively homomorphic ring-LWE masking
O Reparaz, R de Clercq, SS Roy, F Vercauteren, I Verbauwhede
Post-Quantum Cryptography, 233-244, 2016
632016
Compact and Side Channel Secure Discrete Gaussian Sampling.
SS Roy, O Reparaz, F Vercauteren, I Verbauwhede
IACR Cryptol. Eprint Arch. 2014, 591, 2014
62*2014
Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed
SS Roy, C Rebeiro, D Mukhopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 901-909, 2012
582012
Saber on ARM CCA-secure module lattice-based key encapsulation on ARM
A Karmakar, JMB Mera, SS Roy, I Verbauwhede
IACR Transactions on Cryptographic Hardware and Embedded Systems, 243-266, 2018
572018
Constant-time discrete gaussian sampling
A Karmakar, SS Roy, O Reparaz, F Vercauteren, I Verbauwhede
IEEE Transactions on Computers 67 (11), 1561-1571, 2018
472018
Generic Side-channel attacks on CCA-secure lattice-based PKE and KEMs.
P Ravi, SS Roy, A Chattopadhyay, S Bhasin
IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (3), 307-335, 2020
45*2020
Modular hardware architecture for somewhat homomorphic function evaluation
SS Roy, K Järvinen, F Vercauteren, V Dimitrov, I Verbauwhede
International Workshop on Cryptographic Hardware and Embedded Systems, 164-184, 2015
442015
Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms
C Rebeiro, SS Roy, DS Reddy, D Mukhopadhyay
IEEE Transactions on very large scale integration (vlsi) systems 19 (8 …, 2010
432010
Masking ring-LWE
O Reparaz, SS Roy, R De Clercq, F Vercauteren, I Verbauwhede
Journal of Cryptographic Engineering 6 (2), 139-153, 2016
322016
High-speed instruction-set coprocessor for lattice-based key encapsulation mechanism: Saber in hardware
SS Roy, A Basso
IACR Transactions on Cryptographic Hardware and Embedded Systems, 443-466, 2020
302020
HEPCloud: An FPGA-based multicore processor for FV somewhat homomorphic function evaluation
SS Roy, K Järvinen, J Vliegen, F Vercauteren, I Verbauwhede
IEEE Transactions on Computers 67 (11), 1637-1650, 2018
302018
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