| FPGA architecture: Survey and challenges I Kuon, R Tessier, J Rose Foundations and TrendsŪ in Electronic Design Automation 2 (2), 135-253, 2008 | 866 | 2008 |
| Reconfigurable computing for digital signal processing: A survey R Tessier, W Burleson Journal of VLSI signal processing systems for signal, image and video …, 2001 | 567 | 2001 |
| Virtual interconnections for reconfigurable logic systems A Agarwal, J Babb, R Tessier US Patent 5,596,742, 1997 | 305 | 1997 |
| Virtual interconnections for reconfigurable logic systems A Agarwal, J Babb, R Tessier US Patent 5,761,484, 1998 | 285 | 1998 |
| aSOC: A scalable, single-chip communications architecture J Liang, S Swaminathan, R Tessier Proceedings 2000 International Conference on Parallel Architectures and …, 2000 | 259 | 2000 |
| Virtual wires: Overcoming pin limitations in FPGA-based logic emulators J Babb, R Tessier, A Agarwal [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, 142-151, 1993 | 246 | 1993 |
| Reconfigurable computing architectures R Tessier, K Pocek, A DeHon Proceedings of the IEEE 103 (3), 332-354, 2015 | 238 | 2015 |
| Logic emulation with virtual wires J Babb, R Tessier, M Dahl, SZ Hanono, DM Hoki, A Agarwal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1997 | 222 | 1997 |
| Balancing logic utilization and area efficiency in FPGAs R Tessier, H Giza Field-Programmable Logic and Applications: The Roadmap to Reconfigurable …, 2000 | 163 | 2000 |
| Floating point unit generation and evaluation for FPGAs J Liang, R Tessier, O Mencer 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2003 | 146 | 2003 |
| FPGA side channel attacks without physical access C Ramesh, SB Patil, SN Dhanuskodi, G Provelengios, S Pillement, ... 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 121 | 2018 |
| An architecture and compiler for scalable on-chip communication J Liang, A Laffely, S Srinivasan, R Tessier IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (7), 711-726, 2004 | 117 | 2004 |
| A dynamically reconfigurable adaptive viterbi decoder S Swaminathan, R Tessier, D Goeckel, W Burleson Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002 | 110 | 2002 |
| Tolerating operational faults in cluster-based FPGAs V Lakamraju, R Tessier Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000 | 110 | 2000 |
| Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits A Maheshwari, W Burleson, R Tessier IEEE transactions on very large scale integration (VLSI) systems 12 (3), 299-311, 2004 | 107 | 2004 |
| BDD-based logic synthesis for LUT-based FPGAs N Vemuri, P Kalla, R Tessier ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (4 …, 2002 | 96 | 2002 |
| Multicore soft error rate stabilization using adaptive dual modular redundancy R Vadlamani, J Zhao, W Burleson, R Tessier 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 94 | 2010 |
| FlexGrip: A soft GPGPU for FPGAs K Andryc, M Merchant, R Tessier 2013 International Conference on Field-Programmable Technology (FPT), 230-237, 2013 | 93 | 2013 |
| BIST-based delay path testing in FPGA architectures IG Harris, PR Menon, R Tessier Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 932-938, 2001 | 85 | 2001 |
| A reconfigurable, power-efficient adaptive Viterbi decoder R Tessier, S Swaminathan, R Ramaswamy, D Goeckel, W Burleson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (4), 484-488, 2005 | 80 | 2005 |
