CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance U Peralagu, A Alian, V Putcha, A Khaled, R Rodriguez, ...
2019 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2019
62 2019 A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability B Kaczer, J Franco, P Weckx, PJ Roussel, V Putcha, E Bury, M Simicic, ...
Microelectronics Reliability 81, 186-194, 2018
60 2018 Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
47 2017 Origins and implications of increased channel hot carrier variability in nFinFETs B Kaczer, J Franco, M Cho, T Grasser, PJ Roussel, S Tyaginov, M Bina, ...
2015 IEEE International Reliability Physics Symposium, 3B. 5.1-3B. 5.6, 2015
38 2015 Total-Ionizing-Dose Effects and Low-Frequency Noise in 16-nm InGaAs FinFETs With HfO2 /Al2 O3 Dielectrics S Bonaldo, SE Zhao, A O’Hara, M Gorchichko, EX Zhang, S Gerardin, ...
IEEE Transactions on Nuclear Science 67 (1), 210-220, 2019
36 2019 Statistical poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels R Degraeve, S Clima, V Putcha, B Kaczer, P Roussel, D Linten, ...
2015 IEEE International Electron Devices Meeting (IEDM), 5.6. 1-5.6. 4, 2015
30 2015 Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation K Takakura, V Putcha, E Simoen, AR Alian, U Peralagu, N Waldron, ...
IEEE Transactions on Electron Devices 67 (8), 3062-3068, 2020
28 2020 GaN-on-Si mm-wave RF Devices Integrated in a 200mm CMOS Compatible 3-Level Cu BEOL B Parvais, A Alian, U Peralagu, R Rodriguez, S Yadav, A Khaled, ...
2020 IEEE International Electron Devices Meeting (IEDM), 8.1. 1-8.1. 4, 2020
27 2020 Defect profiling in FEFET Si:HfO2 layers BJ O'Sullivan, V Putcha, R Izmailov, V Afanas' ev, E Simoen, T Jung, ...
Applied Physics Letters 117 (20), 203504, 2020
27 2020 The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits B Kaczer, J Franco, P Weckx, PJ Roussel, M Simicic, V Putcha, E Bury, ...
Solid-State Electronics 125, 52-62, 2016
23 2016 Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS J Franco, L Witters, A Vandooren, H Arimura, S Sioncke, V Putcha, A Vais, ...
2017 IEEE International Reliability Physics Symposium (IRPS), 2B-3.1-2B-3.5, 2017
22 2017 Record performance Top-down In0.53 Ga0.47 As vertical nanowire FETs and vertical nanosheets S Ramesh, T Ivanov, V Putcha, A Alian, A Sibaja-Hernandez, ...
2017 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2017
20 2017 Advanced MOSFET variability and reliability characterization array M Simicic, V Putcha, B Parvais, P Weckx, B Kaczer, G Groeseneken, ...
2015 IEEE International Integrated Reliability Workshop (IIRW), 73-76, 2015
20 2015 Total-ionizing-dose effects on InGaAs FinFETs with modified gate-stack SE Zhao, S Bonaldo, P Wang, EX Zhang, N Waldron, N Collaert, V Putcha, ...
IEEE Transactions on Nuclear Science 67 (1), 253-259, 2019
17 2019 Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND A Subirats, A Arreghini, E Capogreco, R Delhougne, CL Tan, A Hikavyy, ...
2017 IEEE International Electron Devices Meeting (IEDM), 21.2. 1-21.2. 4, 2017
16 2017 Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole J Franco, A Vais, S Sioncke, V Putcha, B Kaczer, BS Shie, X Shi, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
16 2016 Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs J Franco, V Putcha, A Vais, S Sioncke, N Waldron, D Zhou, G Rzepa, ...
2017 IEEE International Electron Devices Meeting (IEDM), 7.5. 1-7.5. 4, 2017
15 2017 On the distribution of oxide defect levels in Al2 O3 and HfO2 high-k dielectrics deposited on InGaAs metal-oxide-semiconductor devices studied by capacitance … A Vais, J Franco, D Lin, V Putcha, S Sioncke, A Mocuta, N Collaert, ...
Journal of Applied Physics 121 (14), 144504, 2017
14 2017 On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in IIIV/High- V Putcha, J Franco, A Vais, S Sioncke, B Kaczer, D Linten, ...
IEEE Transactions on Electron Devices 65 (9), 3689-3696, 2018
12 2018 Semiconductor Technologies for next Generation Mobile Communications N Collaert, A Alian, SH Chen, V Deshpande, M Ingels, V Putcha, ...
2018 14th IEEE International Conference on Solid-State and Integrated …, 2018
11 2018 
Dimitri LintenImecGeverifieerd e-mailadres voor imec.be
