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Abhijith Prakash
Abhijith Prakash
Western Digital Technologies, Inc.
Geverifieerd e-mailadres voor purdue.edu
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Covalent Nitrogen Doping and Compressive Strain in MoS2 by Remote N2 Plasma Exposure
A Azcatl, X Qin, A Prakash, C Zhang, L Cheng, Q Wang, N Lu, MJ Kim, ...
Nano Letters, 2016
3982016
Toward Low-Power Electronics: Tunneling Phenomena in Transition Metal Dichalcogenides
S Das*, A Prakash*, R Salazar, J Appenzeller
ACS nano, 2014
2092014
Understanding contact gating in Schottky barrier transistors from 2D channels
A Prakash, H Ilatikhameneh, P Wu, J Appenzeller
Scientific Reports 7, 2017
1122017
Bandgap Extraction and Device Analysis of Ionic Liquid Gated WSe2 Schottky Barrier Transistors
A Prakash, J Appenzeller
ACS Nano 11, 2017
642017
Low-frequency noise in MoSe2 field effect transistors
SR Das, J Kwon, A Prakash, CJ Delker, S Das, DB Janes
Applied Physics Letters 106 (8), 083507, 2015
602015
Reducing post-read disturb in a nonvolatile memory device
A Prakash, A Khandelwal, D Dutta, H Tseng, W Zhao, D Zhao
US Patent 10,726,891, 2020
142020
Countermeasures for first read issue
YC Lien, HY Tseng, D Dutta, A Prakash
US Patent 10,861,537, 2020
112020
Correlating Electronic Transport and 1/f Noise in Field-Effect Transistors
J Kwon, A Prakash, SR Das, DB Janes
Physical Review Applied 10 (6), 064029, 2018
92018
First demonstration of band-to-band tunneling in black phosphorus
P Wu, A Prakash, J Appenzeller
2017 75th Annual Device Research Conference (DRC), 1-2, 2017
92017
Refresh operations for dedicated groups of blocks of memory cells
A Prakash, J Yuan
US Patent 11,043,280, 2021
72021
Ionic gated WSe2 FETs: towards transparent Schottky barriers
A Prakash, S Das, R Mehta, Z Chen, J Appenzeller
72nd Device Research Conference, 129-130, 2014
62014
Reducing post-read disturb in a nonvolatile memory device
A Prakash, A Khandelwal
US Patent 11,139,030, 2021
52021
MEMORY DEVICE WITH IMPROVED ENDURANCE
X Yang, M Higanshitani, A Prakash
US Patent App. 17/403,310, 2023
42023
Temperature and cycling dependent refresh operation for memory cells
A Prakash, VB Shanthakumar, J Yuan
US Patent 11,037,641, 2021
42021
Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines
YC Lien, A Prakash, K Payak, J Yuan, HY Tseng, S Yada, K Isozumi
US Patent 11,758,718, 2023
22023
Read operation or word line voltage refresh operation in memory device with reduced peak current
A Prakash
US Patent 11,501,837, 2022
22022
Refresh operations for memory cells based on susceptibility to read errors
A Prakash, J Yuan
US Patent 11,264,110, 2022
22022
Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate
X Yang, A Prakash, S Mukherjee
US Patent 11,894,067, 2024
12024
Pre-position dummy word line to facilitate write erase capability of memory apparatus
X Yang, A Prakash
US Patent App. 17/665,267, 2023
12023
Memory device that is optimized for operation at different temperatures
A Prakash, X Yang, D Zhao
US Patent App. 17/533,292, 2023
12023
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Artikelen 1–20