| A proposal for energy-efficient cellular neural network based on spintronic devices C Pan, A Naeemi IEEE Transactions on Nanotechnology 15 (5), 820-827, 2016 | 53 | 2016 |
| A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap C Pan, A Naeemi Electron Device Letters, IEEE 35 (2), 250-252, 2014 | 50 | 2014 |
| An expanded benchmarking of beyond-CMOS devices based on Boolean and neuromorphic representative circuits C Pan, A Naeemi IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3 …, 2017 | 49 | 2017 |
| Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network C Pan, A Naeemi IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2 …, 2016 | 47 | 2016 |
| Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node C Pan, P Raghavan, D Yakimets, P Debacker, F Catthoor, N Collaert, ... IEEE Transactions on Electron Devices 62 (10), 3125-3132, 2015 | 46 | 2015 |
| A mixed signal architecture for convolutional neural networks Q Lou, C Pan, J McGuinness, A Horvath, A Naeemi, M Niemier, XS Hu ACM Journal on Emerging Technologies in Computing Systems (JETC) 15 (2), 1-26, 2019 | 29 | 2019 |
| A paradigm shift in local interconnect technology design in the era of nanoscale multigate and gate-all-around devices C Pan, A Naeemi IEEE Electron Device Letters 36 (3), 274-276, 2015 | 29 | 2015 |
| Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node C Pan, P Raghavan, A Ceyhan, F Catthoor, Z Tokei, A Naeemi IEEE Transactions on Electron Devices 62 (5), 1530-1536, 2015 | 27 | 2015 |
| Benchmarking and optimization of spintronic memory arrays YC Liao, C Pan, A Naeemi IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020 | 23 | 2020 |
| Adapting interconnect technology to multigate transistors for optimum performance D Prasad, A Ceyhan, C Pan, A Naeemi IEEE Transactions on Electron Devices 62 (12), 3938-3944, 2015 | 22 | 2015 |
| Nonvolatile spintronic memory array performance benchmarking based on three-terminal memory cell C Pan, A Naeemi IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3 …, 2017 | 18 | 2017 |
| BEOL scaling limits and next generation technology prospects A Naeemi, A Ceyhan, V Kumar, C Pan, RM Iraei, S Rakheja Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 18 | 2014 |
| Device-and system-level performance modeling for graphene pn junction logic C Pan, A Naeemi Thirteenth International Symposium on Quality Electronic Design (ISQED), 262-269, 2012 | 18 | 2012 |
| Performance analysis and enhancement of negative capacitance logic devices based on internally resistive ferroelectrics CS Hsu, C Pan, A Naeemi IEEE Electron Device Letters 39 (5), 765-768, 2018 | 15 | 2018 |
| Beyond-cmos non-boolean logic benchmarking: Insights and future directions C Pan, A Naeemi Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 15 | 2017 |
| Impact of interconnect variability on circuit performance in advanced technology nodes D Prasad, C Pan, A Naeemi 2016 17th International Symposium on Quality Electronic Design (ISQED), 398-404, 2016 | 15 | 2016 |
| Magnetoelectric computational devices C Pan, S Dutta, A Naeemi US Patent 9,979,401, 2018 | 14 | 2018 |
| Complementary logic implementation for antiferromagnet field-effect transistors C Pan, A Naeemi IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 4 …, 2018 | 13 | 2018 |
| System-level variation analysis for interconnection networks at sub-10-nm technology nodes using multiple patterning techniques C Pan, R Baert, I Ciofi, Z Tokei, A Naeemi IEEE Transactions on Electron Devices 62 (7), 2071-2077, 2015 | 13 | 2015 |
| Interconnect design and benchmarking for charge-based beyond-CMOS device proposals C Pan, A Naeemi IEEE Electron Device Letters 37 (4), 508-511, 2016 | 11 | 2016 |
Azad NaeemiProfessor of Electrical and Computer Engineering, Georgia Institute of TechnologyVerified email at gatech.edu
