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Meng-Fan Chang
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A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability
SS Sheu, MF Chang, KF Lin, CW Wu, YS Chen, PF Chiu, CC Kuo, ...
2011 IEEE International Solid-State Circuits Conference, 200-202, 2011
2562011
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496, 2018
2352018
Neuro-inspired computing chips
W Zhang, B Gao, J Tang, P Yao, S Yu, MF Chang, HJ Yoo, H Qian, H Wu
Nature electronics 3 (7), 371-382, 2020
2162020
24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors
CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019
2022019
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors
WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018
1882018
24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning
X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019
1672019
Differential sensing and TSV timing control scheme for 3D-IC
WC Wu, YH Chen, MF Chang
US Patent 7,969,193, 2011
1562011
Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications
PF Chiu, MF Chang, CW Wu, CH Chuang, SS Sheu, YS Chen, MJ Tsai
IEEE Journal of Solid-State Circuits 47 (6), 1483-1496, 2012
1512012
A 130 mV SRAM with expanded write and read margins for subthreshold applications
MF Chang, SW Chang, PW Chou, WC Wu
IEEE Journal of Solid-State Circuits 46 (2), 520-529, 2010
1502010
Ambient energy harvesting nonvolatile processors: From circuit to system
Y Liu, Z Li, H Li, Y Wang, X Li, K Ma, S Li, MF Chang, S John, Y Xie, J Shu, ...
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
1392015
Fast-write resistive RAM (RRAM) for embedded applications
SS Sheu, KH Cheng, MF Chang, PC Chiang, WP Lin, HY Lee, PS Chen, ...
IEEE Design & Test of Computers 28 (1), 64-71, 2010
1312010
15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices
CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020
1302020
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme
MF Chang, JJ Wu, TF Chien, YC Liu, TC Yang, WC Shen, YC King, CJ Lin, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
1252014
A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications
PF Chiu, MF Chang, SS Sheu, KF Lin, PC Chiang, CW Wu, WP Lin, ...
2010 Symposium on VLSI Circuits, 229-230, 2010
1192010
33.2 A fully integrated analog ReRAM based 78.4 TOPS/W compute-in-memory chip with fully parallel MAC computing
Q Liu, B Gao, P Yao, D Wu, J Chen, Y Pang, W Zhang, Y Liao, CX Xue, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 500-502, 2020
1092020
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
WH Chen, C Dou, KX Li, WY Lin, PY Li, JH Huang, JH Wang, WC Wei, ...
Nature Electronics 2 (9), 420-428, 2019
1092019
15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips
X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2020
1052020
Nonvolatile memory design based on ferroelectric FETs
S George, K Ma, A Aziz, X Li, A Khan, S Salahuddin, MF Chang, S Datta, ...
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
1052016
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination …
Y Liu, Z Wang, A Lee, F Su, CP Lo, Z Yuan, CC Lin, Q Wei, Y Wang, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 84-86, 2016
1022016
Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC
MF Chang, PF Chiu, SS Sheu
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 197-203, 2011
1002011
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