| Standard Model physics at the HL-LHC and HE-LHC P Azzi, S Farry, P Nason, A Tricoli, D Zeppenfeld, RA Khalek, J Alimena, ... arXiv preprint arXiv:1902.04070, 2019 | 228 | 2019 |
| Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime F Jazaeri, L Barbut, A Koukab, JM Sallese Solid-State Electronics 82, 103-110, 2013 | 150 | 2013 |
| Cryogenic MOS transistor model A Beckers, F Jazaeri, C Enz IEEE Transactions on Electron Devices 65 (9), 3617-3625, 2018 | 140 | 2018 |
| Semiconductor spin qubits G Burkard, TD Ladd, A Pan, JM Nichol, JR Petta Reviews of Modern Physics 95 (2), 025003, 2020 | 137 | 2020 |
| Characterization and modeling of 28-nm bulk CMOS technology down to 4.2 K A Beckers, F Jazaeri, C Enz IEEE Journal of the Electron Devices Society 6, 1007-1018, 2018 | 136 | 2018 |
| Theoretical limit of low temperature subthreshold swing in field-effect transistors A Beckers, F Jazaeri, C Enz IEEE Electron Device Letters 41 (2), 276-279, 2019 | 119 | 2019 |
| A review on quantum computing: From qubits to front-end electronics and cryogenic MOSFET physics F Jazaeri, A Beckers, A Tajalli, JM Sallese 2019 MIXDES-26th International Conference" Mixed Design of Integrated …, 2019 | 98 | 2019 |
| Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures A Beckers, F Jazaeri, H Bohuslavskyi, L Hutin, S De Franceschi, C Enz Solid-State Electronics 159, 106-115, 2019 | 91 | 2019 |
| Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra thin body SOI: An experimentally calibrated simulation study of device performance A Saeidi, F Jazaeri, I Stolichnov, AM Ionescu IEEE Transactions on Electron Devices 63 (12), 4678-4684, 2016 | 91 | 2016 |
| Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing A Beckers, F Jazaeri, A Ruffino, C Bruschini, A Baschirotto, C Enz 2017 47th European Solid-State Device Research Conference (ESSDERC), 62-65, 2017 | 83 | 2017 |
| Negative capacitance as performance booster for tunnel FETs and MOSFETs: an experimental study A Saeidi, F Jazaeri, F Bellando, I Stolichnov, GV Luong, QT Zhao, S Mantl, ... IEEE electron device letters 38 (10), 1485-1488, 2017 | 70 | 2017 |
| Physical model of low-temperature to cryogenic threshold voltage in MOSFETs A Beckers, F Jazaeri, A Grill, S Narasimhamoorthy, B Parvais, C Enz IEEE Journal of the Electron Devices Society 8, 780-788, 2020 | 56 | 2020 |
| Modeling nanowire and double-gate junctionless field-effect transistors F Jazaeri, JM Sallese Cambridge University Press, 2018 | 56 | 2018 |
| Modeling and design space of junctionless symmetric DG MOSFETs with long channel F Jazaeri, L Barbut, JM Sallese IEEE transactions on electron devices 60 (7), 2120-2127, 2013 | 53 | 2013 |
| A common core model for junctionless nanowires and symmetric double-gate FETs JM Sallese, F Jazaeri, L Barbut, N Chevillon, C Lallement IEEE transactions on electron devices 60 (12), 4277-4280, 2013 | 52 | 2013 |
| Cryogenic MOSFET threshold voltage model A Beckers, F Jazaeri, C Enz ESSDERC 2019-49th European Solid-State Device Research Conference (ESSDERC …, 2019 | 49 | 2019 |
| Characterization of gigarad total ionizing dose and annealing effects on 28-nm bulk MOSFETs CM Zhang, F Jazaeri, A Pezzotta, C Bruschini, G Borghello, F Faccio, ... IEEE Transactions on Nuclear Science 64 (10), 2639-2647, 2017 | 49 | 2017 |
| Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing A Beckers, F Jazaeri, H Bohuslavskyi, L Hutin, S De Franceschi, C Enz 2018 Joint International EUROSOI Workshop and International Conference on …, 2018 | 40 | 2018 |
| On performance scaling and speed of junctionless transistors A Koukab, F Jazaeri, JM Sallese Solid-State Electronics 79, 18-21, 2013 | 38 | 2013 |
| Characterization and modeling of Gigarad-TID-induced drain leakage current of 28-nm bulk MOSFETs CM Zhang, F Jazaeri, G Borghello, F Faccio, S Mattiazzo, A Baschirotto, ... IEEE Transactions on Nuclear Science 66 (1), 38-47, 2018 | 36 | 2018 |
Christian EnzEcole Polytechnique Fédérale de Lausanne (EPFL)Verified email at epfl.ch
