Alessio Spessot
Alessio Spessot
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Fabrication by electron beam induced deposition and transmission electron microscopic characterization of sub- freestanding Pt nanowires
S Frabboni, GC Gazzadi, L Felisari, A Spessot
Applied physics letters 88 (21), 213116, 2006
732006
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
512017
System and method for current sensing
R Goodfellow, D Susak
US Patent 6,559,684, 2003
482003
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE International Electron Devices Meeting (IEDM), 37.4. 1-37.4. 4, 2017
412017
TEM study of annealed Pt nanostructures grown by electron beam-induced deposition
S Frabboni, GC Gazzadi, A Spessot
Physica E: Low-dimensional Systems and Nanostructures 37 (1-2), 265-269, 2007
392007
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
332016
Role of mechanical stress in the resistance drift of Ge2Sb2Te5 films and phase change memories
M Rizzi, A Spessot, P Fantini, D Ielmini
Applied Physics Letters 99 (22), 223513, 2011
332011
Variability effects on the VT distribution of nanoscale NAND Flash memories
A Spessot, A Calderoni, P Fantini, AS Spinelli, CM Compagnoni, F Farina, ...
2010 IEEE International Reliability Physics Symposium, 970-974, 2010
292010
Method for tuning the effective work function of a gate structure in a semiconductor device
T Kauerauf, A Spessot, C Caillat
US Patent 9,076,726, 2015
282015
The FAST module: An add-on unit for driving commercial scanning probe microscopes at video rate and beyond
F Esch, C Dri, A Spessot, C Africh, G Cautero, D Giuressi, R Sergo, ...
Review of Scientific Instruments 82 (5), 053702, 2011
262011
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
252018
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
252017
Low track height standard cell design in iN7 using scaling boosters
SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
212017
Method for determination of the displacement field in patterned nanostructures by TEM/CBED analysis of split high‐order Laue zone line profiles
A Spessot, S Frabboni, R Balboni, A Armigliato
Journal of microscopy 226 (2), 140-155, 2007
202007
Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels
E Bury, B Kaczer, D Linten, L Witters, H Mertens, N Waldron, X Zhou, ...
2016 IEEE International Electron Devices Meeting (IEDM), 15.6. 1-15.6. 4, 2016
182016
An analysis of temperature impact on MOSFET mismatch
S Mennillo, A Spessot, L Vendrame, L Bortesi
2009 IEEE International Conference on Microelectronic Test Structures, 56-61, 2009
172009
Low-power DRAM-compatible replacement gate high-k/metal gate stacks
R Ritzenthaler, T Schram, E Bury, A Spessot, C Caillat, V Srividya, ...
Solid-state electronics 84, 22-27, 2013
152013
Compact modeling of variability effects in nanoscale NAND flash memories
A Spessot, CM Compagnoni, F Farina, A Calderoni, AS Spinelli, P Fantini
IEEE transactions on electron devices 58 (8), 2302-2309, 2011
152011
Transmission electron microscopy characterization and sculpting of sub- Si–O–C freestanding nanowires grown by electron beam induced deposition
S Frabboni, GC Gazzadi, A Spessot
Applied physics letters 89 (11), 113108, 2006
152006
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3. 1-18.3. 4, 2018
142018
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