| Scan based side channel attacks on stream ciphers and their counter-measures M Agrawal, S Karmakar, D Saha, D Mukhopadhyay Progress in Cryptology-INDOCRYPT 2008: 9th International Conference on …, 2008 | 76 | 2008 |
| Power level distributions of radio base station equipment and user devices in a 3G mobile communication network in India and the impact on assessments of realistic RF EMF exposure P Joshi, M Agrawal, B Thors, D Colombi, A Kumar, C Törnevik IEEE Access 3, 1051-1059, 2015 | 30 | 2015 |
| Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs M Agrawal, K Chakrabarty IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 28 | 2015 |
| Test-time optimization in NOC-based manycore SOCs using multicast routing M Agrawal, K Chakrabarty VLSI Test Symposium (VTS), 2014 IEEE 32nd, 1-6, 2014 | 27 | 2014 |
| Test-cost optimization and test-flow selection for 3D-stacked ICs M Agrawal, K Chakrabarty VLSI Test Symposium (VTS), 2013 IEEE 31st, 1-6, 2013 | 22 | 2013 |
| Test and design-for-testability solutions for 3D integrated circuits K Chakrabarty, M Agrawal, S Deutsch, B Noia, R Wang, F Ye IPSJ Transactions on System LSI Design Methodology 7, 56-73, 2014 | 20 | 2014 |
| A dynamic programming solution for optimizing test delivery in multicore SOCs M Agrawal, M Richter, K Chakrabarty Test Conference (ITC), 2012 IEEE International, 1-10, 2012 | 19 | 2012 |
| Test-Delivery Optimization in Manycore SOCs M Agrawal, M Richter, K Chakrabarty Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2014 | 12 | 2014 |
| Sealing device and positioning device using the same T Nakamura, N Saji US Patent App. 10/013,352, 2002 | 9* | 2002 |
| Reuse-based optimization for prebond and post-bond testing of 3-D-stacked ICs M Agrawal, K Chakrabarty, R Widialaksono IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 7 | 2014 |
| Simultaneous task scheduling and resource binding for digital print automation M Agrawal, K Chakrabarty, J Zeng, IJ Lin, G Dispoto IIE Annual Conference. Proceedings, 1, 2011 | 7 | 2011 |
| Micro-sector cache: improving space utilization in sectored DRAM caches M Chaudhuri, M Agrawal, J Gaur, S Subramoney ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 1-29, 2017 | 6 | 2017 |
| The hype, myths, and realities of testing 3D integrated circuits R Wang, S Deutsch, M Agrawal, K Chakrabarty 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 6 | 2016 |
| A distributed, reconfigurable, and reusable BIST infrastructure for test and diagnosis of 3-D-Stacked ICs M Agrawal, K Chakrabarty, B Eklow IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 6 | 2015 |
| Digital print workflow optimization under due-dates, opportunity cost and resource constraints M Agrawal, Q Duan, K Chakrabarty, J Zeng, IJ Lin, G Dispoto, YS Lee 2011 9th IEEE International Conference on Industrial Informatics, 86-92, 2011 | 5 | 2011 |
| A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs M Agrawal, K Chakrabarty, B Eklow 2014 International Test Conference, 1-10, 2014 | 2 | 2014 |
| 2015 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 34 G Agosta, M Agrawal, N Ahmed, M Ahrens, VB Ajabshir, F Akopyan, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | | 2015 |
| Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs M Agrawal Duke University, 2014 | | 2014 |
| A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs M Agrawal, K Chakrabarty Test Conference (ITC), 2013 IEEE International, 1-10, 2013 | | 2013 |
| Real-Time and Online Digital-Print Factory Workflow Optimization Q Duan, M Agrawal, K Chakrabarty, J Zeng, G Dispoto | | 2012 |
