| A general decomposition for reversible logic M Perkowski, L Jozwiak, P Kerntopf, A Mishchenko, A Al-Rabadi, ... | 247 | 2001 |
| Design of full-adder with reversible gates MMHA Khan International Conference on Computer and Information Technology, Dhaka …, 2002 | 147 | 2002 |
| Quantum ternary parallel adder/subtractor with partially-look-ahead carry MHA Khan, MA Perkowski Journal of Systems Architecture 53 (7), 453-464, 2007 | 112 | 2007 |
| On universality of general reversible multiple-valued logic gates P Kerntopf, MA Perkowski, MHA Khan Proceedings. 34th International Symposium on Multiple-Valued Logic, 68-73, 2004 | 101 | 2004 |
| Terary GFSOP minimization using kronecker decision diagrams and their synthesis with quantum cascades MHA Khan, MA Perkowski, MR Khan, P Kerntopf Journal of Multiple Valued Logic and Soft Computing 11 (5/6), 567, 2005 | 98 | 2005 |
| Multi-output Galois field sum of products synthesis with new quantum cascades MHA Khan, MA Perkowski, P Kerntopf 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings …, 2003 | 86 | 2003 |
| Design of Reversible/Quantum Ternary Multiplexer and Demultiplexer. MHA Khan Engineering letters 13 (3), 2006 | 60 | 2006 |
| Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates MHA Khan, M Perkowski Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No …, 2004 | 60 | 2004 |
| GF (4) based synthesis of quaternary reversible/quantum logic circuits MHA Khan, MA Perkowski 37th International Symposium on Multiple-Valued Logic (ISMVL'07), 11-11, 2007 | 45 | 2007 |
| Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products] MHA Khan, MA Perkowski, MR Khan Proceedings. 34th International Symposium on Multiple-Valued Logic, 58-67, 2004 | 44 | 2004 |
| Reversible realization of quaternary decoder, multiplexer, and demultiplexer circuits MHA Khan 38th International Symposium on Multiple Valued Logic (ismvl 2008), 208-213, 2008 | 43 | 2008 |
| Quantum realization of ternary encoder and decoder MHA Khan, M Perkowski Proc. 7th Int. Symp. Representations and Methodology of Future Computing …, 2005 | 39 | 2005 |
| Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits. MHA Khan Engineering Letters 16 (1), 2008 | 38 | 2008 |
| Minimization of quaternary Galois field sum of products expression for multi-output quaternary logic function using quaternary Galois field decision diagram MHA Khan, NK Siddika, MA Perkowski 38th International Symposium on Multiple Valued Logic (ismvl 2008), 125-130, 2008 | 37 | 2008 |
| Synthesis of quaternary reversible/quantum comparators MHA Khan Journal of Systems Architecture 54 (10), 977-982, 2008 | 36 | 2008 |
| A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry MHA Khan Journal of Systems Architecture 54 (12), 1113-1121, 2008 | 35 | 2008 |
| Quantum realization of some ternary circuits using Muthukrishnan-Stroud gates AI Khan, N Nusrat, SM Khan, M Hasan, MHA Khan 37th International Symposium on Multiple-Valued Logic (ISMVL'07), 20-20, 2007 | 35 | 2007 |
| Multi-output ESOP synthesis with cascades of new reversible gate family MHA Khan, M Perkowski | 35 | 2003 |
| Design of reversible synchronous sequential circuits using pseudo Reed-Muller expressions MHA Khan IEEE transactions on very large scale integration (VLSI) systems 22 (11 …, 2013 | 34 | 2013 |
| Synthesis of reversible synchronous counters MHA Khan, M Perkowski 2011 41st IEEE International Symposium on Multiple-Valued Logic, 242-247, 2011 | 30 | 2011 |
Pawel KerntopfProfessor, Warsaw University of TechnologyGeverifieerd e-mailadres voor ii.pw.edu.pl
