Dan Mocuta
Dan Mocuta
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Method of preventing surface roughening during hydrogen prebake of SiGe substrates
H Chen, DM Mocuta, RJ Murphy, SW Bedell, DK Sadana
US Patent 6,958,286, 2005
2532005
MOSFET with super-steep retrograded island
H Zhu, E Leobandung, AC Mocuta, DM Mocuta
US Patent 7,723,750, 2010
2182010
Structure and method for manufacturing MOSFET with super-steep retrograded island
H Zhu, E Leobandung, AC Mocuta, DM Mocuta
US Patent 7,268,049, 2007
1302007
High performance CMOS device structure with mid-gap metal gate
AC Mocuta, M Ieong, RS Amos, DC Boyd, DM Mocuta, H Chen
US Patent 6,916,698, 2005
1292005
Strained Si CMOS (SS CMOS) technology: opportunities and challenges
K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, ...
Solid-State Electronics 47 (7), 1133-1139, 2003
1232003
Chemical treatment to retard diffusion in a semiconductor overlayer
KK Chan, H Chen, MA Gribelyuk, JR Holt, WH Lee, RM Mitchell, RT Mo, ...
US Patent 7,071,103, 2006
1192006
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
H Mertens, R Ritzenthaler, A Hikavyy, MS Kim, Z Tao, K Wostyn, SA Chew, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
942016
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
D Chidambarrao, AC Mocuta, DM Mocuta, C Radens
US Patent 7,691,698, 2010
942010
Test Structure and e-Beam Inspection Methodology for In-line Detection of (Non-visual) Missing Spacer Defects
OD Patterson, K Wu, D Mocuta, K Nafisi
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 48-53, 2007
822007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
B Walsh, H Utomo, E Leobandung, A Mahorowala, D Mocuta, K Miyamoto, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 170-171, 2006
812006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005
782005
High performance CMOS device structure with mid-gap metal gate
AC Mocuta, M Ieong, RS Amos, DC Boyd, DM Mocuta, H Chen
US Patent 6,762,469, 2004
692004
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4…, 2005
622005
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ...
2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016
602016
High performance 32nm SOI CMOS with high-k/metal gate and 0.149m2SRAM and ultra low-k back end with eleven levels of copper
B Greene, Q Liang, K Amarnath, Y Wang, J Schaeffer, M Cai, Y Liang, ...
2009 Symposium on VLSI Technology, 140-141, 2009
592009
Adsorbate–adsorbate repulsions—the coverage dependence of the adsorption structure of CO on Cu (110) as studied by electron‐stimulated desorption ion angular distribution
J Ahner, D Mocuta, RD Ramsier, JT Yates Jr
The Journal of chemical physics 105 (15), 6553-6559, 1996
511996
Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D
BH Lee, A Mocuta, S Bedell, H Chen, D Sadana, K Rim, P O'Neil, R Mo, ...
Digest. International Electron Devices Meeting,, 946-948, 2002
502002
N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers
D Chidambarrao, E Leobandung, AC Mocuta, DM Mocuta, DM Onsongo, ...
US Patent App. 11/307,224, 2008
462008
Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition
L Witters, H Arimura, F Sebaai, A Hikavyy, AP Milenin, R Loo, ...
IEEE transactions on electron devices 64 (11), 4587-4593, 2017
432017
InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature
A Alian, Y Mols, CCM Bordallo, D Verreck, A Verhulst, A Vandooren, ...
Applied Physics Letters 109 (24), 243502, 2016
432016
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