Pierce I-Jen Chuang
Pierce I-Jen Chuang
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Pact: Parameterized clipping activation for quantized neural networks
J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ...
arXiv preprint arXiv:1805.06085, 2018
A scalable multi-TeraOPS deep learning processor core for AI trainina and inference
B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
2018 IEEE Symposium on VLSI Circuits, 35-36, 2018
Accurate and Efficient 2-bit Quantized Neural Networks.
J Choi, S Venkataramani, V Srinivasan, K Gopalakrishnan, Z Wang, ...
MLSys, 2019
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection
MS Floyd, PJ Restle, MA Sperling, P Owczarczyk, EJ Fluhr, J Friedrich, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 444-445, 2017
A low-power high-performance single-cycle tree-based 64-bit binary comparator
P Chuang, D Li, M Sachdev
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (2), 108-112, 2012
Constant delay logic style
P Chuang, D Li, M Sachdev
IEEE transactions on very large scale integration (VLSI) systems 21 (3), 554-565, 2012
Bridging the accuracy gap for 2-bit quantized neural networks (qnn)
J Choi, PIJ Chuang, Z Wang, S Venkataramani, V Srinivasan, ...
arXiv preprint arXiv:1807.06964, 2018
Comparative analysis and study of metastability on high-performance flip-flops
D Li, P Chuang, M Sachdev
2010 11th international symposium on quality electronic design (ISQED), 853-860, 2010
Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errors
S Jain, S Venkataramani, V Srinivasan, J Choi, P Chuang, L Chang
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
A 167-ps 2.34-mW single-cycle 64-bit binary tree comparator with constant-delay logic in 65-nm CMOS
I Pierce, J Chuang, M Sachdev, VC Gaudet
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (1), 160-171, 2013
Design and analysis of metastable-hardened flip-flops in sub-threshold region
D Li, I Pierce, J Chuang, D Nairn, M Sachdev
IEEE/ACM International Symposium on Low Power Electronics and Design, 157-162, 2011
Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic
P Chuang, D Li, M Sachdev
2009 IEEE International Symposium on Circuits and Systems, 3038-3041, 2009
26.2 Power supply noise in a 22nm z13™ microprocessor
P Chuang, C Vezyrtzis, D Pathak, R Rizzolo, T Webel, T Strach, ...
Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 438-439, 2017
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops
D Li, D Rennie, P Chuang, D Nairn, M Sachdev
2011 12th International Symposium on Quality Electronic Design, 1-8, 2011
Viterbi-based pruning for sparse matrix with fixed and high index compression ratio
D Lee, D Ahn, T Kim, PI Chuang, JJ Kim
International Conference on Learning Representations, 2018
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor
C Vezyrtzis, T Strach, I Pierce, J Chuang, P Lobo, R Rizzolo, T Webel, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 300-302, 2018
The 24-core POWER9 processor with adaptive clocking, 25-Gb/s accelerator links, and 16-Gb/s PCIe Gen4
C Gonzalez, M Floyd, E Fluhr, P Restle, D Dreps, M Sperling, R Rao, ...
IEEE Journal of Solid-State Circuits 53 (1), 91-101, 2017
One weight bitwidth to rule them all
TW Chin, I Pierce, J Chuang, V Chandra, D Marculescu
European Conference on Computer Vision, 85-103, 2020
A scalable multi-TeraOPS core for AI training and inference
S Shukla, B Fleischer, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
IEEE Solid-State Circuits Letters 1 (12), 217-220, 2018
IBM z14: Processor characterization and power management for high-reliability mainframe systems
C Berry, D Wolpert, C Vezrytzis, R Rizzolo, S Carey, Y Maroz, H Shi, ...
IEEE Journal of Solid-State Circuits 54 (1), 121-132, 2018
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