FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface M Lee, W Tang, B Xue, J Wu, M Ma, Y Wang, Y Liu, D Fan, V Narayanan, ...
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
21 2020 Yoloc: deploy large-scale neural network by rom-based computing-in-memory using residual branch on a chip Y Chen, G Yin, Z Tan, M Lee, Z Yang, Y Liu, H Yang, K Ma, X Li
Proceedings of the 59th ACM/IEEE Design Automation Conference, 1093-1098, 2022
12 2022 SAMBA: Single-ADC multi-bit accumulation compute-in-memory using nonlinearity-compensated fully parallel analog adder tree Y Chen, G Yin, M Zhou, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
4 2023 FeFET-based logic-in-memory supporting SA-free write-back and fully dynamic access with reduced bitline charging activity and recycled bitline charge W Tang, M Lee, J Wu, Y Xu, Y Yu, Y Liu, K Ni, Y Wang, H Yang, ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
3 2023 FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (4), 1605-1609, 2022
3 2022 Hidden-ROM: A compute-in-ROM architecture to deploy large-scale neural networks on chip with flexible and scalable post-fabrication task transfer capability Y Chen, G Yin, M Lee, W Tang, Z Yang, Y Liu, H Yang, X Li
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
2 2022 Victor: A variation-resilient approach using cell-clustered charge-domain computing for high-density high-throughput MLC CiM M Lee, W Tang, Y Chen, J Wu, H Zhong, Y Xu, Y Liu, H Yang, ...
2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023
1 2023 A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface G Yin, M Zhou, Y Chen, W Tang, Z Yang, M Lee, X Du, J Yue, J Liu, ...
arXiv preprint arXiv:2212.04320, 2022
1 2022 FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li
arXiv preprint arXiv:2205.11088, 2022
1 2022 ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns Y Chen, G Yin, H Zhong, M Lee, H Yang, S George, V Narayanan, X Li
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 153-158, 2024
2024 Compute-in-memory devices, neural network accelerators, and electronic devices X Li, G Yin, Y Chen, L Cheong, L Tianyu, W Tang, LEE Mingyen, DU Xirui, ...
US Patent App. 18/342,917, 2024
2024 Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm G Yin, Y Chen, M Zhou, W Tang, M Lee, Z Yang, T Liao, X Du, ...
IEEE Journal of Solid-State Circuits, 2023
2023 GRAPHIC: Gather And Process Harmoniously In the Cache with High Parallelism and Flexibility Y Chen, M Lee, G Dai, M Zhou, N Challapalle, T Wang, Y Yu, Y Liu, ...
IEEE Transactions on Emerging Topics in Computing, 2023
2023 GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph Y Chen, G Dai, M Zhou, M Lee, N Challapalle, G Yin, Z Yang, Y Liu, ...
arXiv preprint arXiv:2208.08600, 2022
2022 
