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Sudhakar Yalamanchili
Sudhakar Yalamanchili
Georgia Institute of Technology
Verified email at stanford.edu
Title
Cited by
Cited by
Year
Interconnection networks
J Duato, S Yalamanchili, L Ni
Morgan Kaufmann, 2003
33152003
Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory
D Kim, J Kung, S Chai, S Yalamanchili, S Mukhopadhyay
ACM SIGARCH Computer Architecture News 44 (3), 380-392, 2016
5052016
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems
GF Diamos, AR Kerr, S Yalamanchili, N Clark
Proceedings of the 19th international conference on Parallel architectures …, 2010
3422010
Adaptive routing protocols for hypercube interconnection networks
PT Gaughan, S Yalamanchili
Computer 26 (5), 12-23, 1993
2651993
Harmony: an execution model and runtime for heterogeneous many core systems
GF Diamos, S Yalamanchili
Proceedings of the 17th international symposium on High performance …, 2008
2492008
A family of fault-tolerant routing protocols for direct multiprocessor networks
PT Gaughan, S Yalamanchili
IEEE Transactions on Parallel and Distributed Systems 6 (5), 482-497, 1995
2341995
On adaptive resource allocation for complex real-time applications
D Rosu, K Schwan, S Yalamanchili, R Jha
Proceedings Real-Time Systems Symposium, 320-329, 1997
2221997
A characterization and analysis of ptx kernels
A Kerr, G Diamos, S Yalamanchili
2009 IEEE international symposium on workload characterization (IISWC), 3-12, 2009
1772009
Modeling GPU-CPU workloads and systems
A Kerr, G Diamos, S Yalamanchili
Proceedings of the 3rd workshop on general-purpose computation on graphics …, 2010
1542010
Keeneland: Bringing heterogeneous GPU computing to the computational science community
JS Vetter, R Glassbrook, J Dongarra, K Schwan, B Loftis, S McNally, ...
Computing in Science & Engineering 13 (05), 90-95, 2011
1532011
Introductory VHDL: from simulation to synthesis
S Yalamanchili
Prentice Hall PTR, 2000
1392000
An energy efficient cache design using spin torque transfer (STT) RAM
M Rasquinha, D Choudhary, S Chatterjee, S Mukhopadhyay, ...
Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010
1342010
Kernel weaver: Automatically fusing database primitives for efficient gpu computation
H Wu, G Diamos, S Cadambi, S Yalamanchili
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 107-118, 2012
1302012
Power constrained design of multiprocessor interconnection networks
CS Patel, SM Chai, S Yalamanchili, DE Schimmel
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
1131997
SIMD re-convergence at thread frontiers
G Diamos, B Ashbaugh, S Maiyuran, A Kerr, H Wu, S Yalamanchili
Proceedings of the 44th annual ieee/acm international symposium on …, 2011
1122011
Characterization and analysis of dynamic parallelism in unstructured GPU applications
J Wang, S Yalamanchili
2014 IEEE International Symposium on Workload Characterization (IISWC), 51-60, 2014
1082014
Red fox: An execution environment for relational query processing on gpus
H Wu, G Diamos, T Sheard, M Aref, S Baxter, M Garland, S Yalamanchili
Proceedings of Annual IEEE/ACM International Symposium on Code Generation …, 2014
1022014
MMR: A high-performance multimedia router-Architecture and design trade-offs
J Duato, S Yalamanchili, MB Caminero, D Love, FJ Quiles
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
951999
Power modeling for GPU architectures using McPAT
J Lim, NB Lakshminarayana, H Kim, W Song, S Yalamanchili, W Sung
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (3 …, 2014
902014
VHDL starter's guide
S Yalamanchili
Prentice Hall PTR, 1997
891997
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