Pei Luo
Pei Luo
Amazon Lab126
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A statistical model for higher order DPA on masked devices
AA Ding, L Zhang, Y Fei, P Luo
International Workshop on Cryptographic Hardware and Embedded Systems, 147-169, 2014
472014
Side-channel power analysis of a GPU AES implementation
C Luo, Y Fei, P Luo, S Mukherjee, D Kaeli
2015 33rd IEEE International Conference on Computer Design (ICCD), 281-288, 2015
462015
Reliable and secure memories based on algebraic manipulation detection codes and robust error correction
S Ge, Z Wang, M Karpovsky, P Luo
Proc. Int. Depend Symp, 2013
262013
Differential Fault Analysis of SHA3-224 and SHA3-256
P Luo, Y Fei, L Zhang, AA Ding
FDTC 2016 - Thirteenth Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016
212016
Side-Channel Analysis of MAC-Keccak Hardware Implementations
P Luo, Y Fei, X Fang, AA Ding, DR Kaeli, M Leeser
HASP '15, Proceedings of the Fourth Workshop on Hardware and Architectural …, 2015
182015
Hardware implementation of secure shamir's secret sharing scheme
P Luo, AYL Lin, Z Wang, M Karpovsky
2014 IEEE 15th International Symposium on High-Assurance Systems Engineering …, 2014
162014
Power Analysis Attack on Hardware Implementation of MAC-Keccak on FPGAs
P Luo, Y Fei, X Fang, AA Ding, M Leeser, DR Kaeli
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014
162014
Side-channel Power Analysis of Different Protection Schemes Against Fault Attacks on AES
P Luo, Y Fei, L Zhang, AA Ding
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014
152014
Towards secure cryptographic software implementation against side-channel power analysis attacks
P Luo, L Zhang, Y Fei, AA Ding
2015 IEEE 26th International Conference on Application-specific Systems …, 2015
132015
Algebraic fault analysis of SHA-3 under relaxed fault models
P Luo, K Athanasiou, Y Fei, T Wahl
IEEE Transactions on Information Forensics and Security 13 (7), 1752-1761, 2018
122018
Power Analysis Attack of an AES GPU Implementation
C Luo, Y Fei, L Zhang, AA Ding, P Luo, S Mukherjee, D Kaeli
Journal of Hardware and Systems Security 2 (1), 69-82, 2018
122018
Concurrent error detection for reliable SHA-3 design
P Luo, C Li, Y Fei
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 39-44, 2016
112016
Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs)
T Swamy, N Shah, P Luo, Y Fei, D Kaeli
Proceedings of the Third Workshop on Hardware and Architectural Support for …, 2014
112014
Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes
S Ge, Z Wang, P Luo, M Karpovsky
Proceedings of the 2nd International Workshop on Hardware and Architectural …, 2013
112013
Algebraic Fault Analysis of SHA-3
P Luo, K Athanasiou, Y Fei, T Wahl
Design, Automation and Test in Europe (DATE), 2017, 2017
102017
System Clock and Power Supply Cross-Checking for Glitch Detection
P Luo, C Luo, Y Fei
Cryptology ePrint Archive, Report 2016/968, 2016
82016
A high reliable SOC on-board computer based on Leon3
L Pei, Z Jian
2012 IEEE International Conference on Computer Science and Automation …, 2012
82012
Balance power leakage to fight against side-channel analysis at gate level in FPGAs
X Fang, P Luo, Y Fei, M Leeser
2015 IEEE 26th International Conference on Application-specific Systems …, 2015
72015
Differential Fault Analysis of SHA-3 Under Relaxed Fault Models
P Luo, Y Fei, L Zhang, AA Ding
Journal of Hardware and Systems Security 1 (2), 156-172, 2017
62017
Faulty Clock Detection for Crypto Circuits Against Differential Fault Analysis Attack.
P Luo, Y Fei
IACR Cryptol. ePrint Arch. 2016, 967, 2016
62016
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Artikelen 1–20