| Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications DK Mohata, R Bijesh, S Mujumdar, C Eaton, R Engel-Herbert, T Mayer, ... 2011 International Electron Devices Meeting, 33.5. 1-33.5. 4, 2011 | 134 | 2011 |
| Barrier-engineered arsenide–antimonide heterojunction tunnel FETs with enhanced drive current D Mohata, B Rajamohanan, T Mayer, M Hudait, J Fastenau, D Lubyshev, ... IEEE Electron Device Letters 33 (11), 1568-1570, 2012 | 116 | 2012 |
| Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio DK Mohata, R Bijesh, Y Zhu, MK Hudait, R Southwick, Z Chbili, ... 2012 Symposium on VLSI technology (VLSIT), 53-54, 2012 | 81 | 2012 |
| Demonstration of In 0.9 Ga 0.1 As/GaAs 0.18 Sb 0.82 near broken-gap tunnel FET with I ON= 740μA/μm, G M= 70μS/μm and gigahertz switching performance at V Ds= 0.5 V R Bijesh, H Liu, H Madan, D Mohata, W Li, NV Nguyen, D Gundlach, ... 2013 IEEE International Electron Devices Meeting, 28.2. 1-28.2. 4, 2013 | 76 | 2013 |
| Electrical noise in heterojunction interband tunnel FETs R Pandey, B Rajamohanan, H Liu, V Narayanan, S Datta IEEE Transactions on Electron Devices 61 (2), 552-560, 2013 | 65 | 2013 |
| 0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6Tunnel FET B Rajamohanan, R Pandey, V Chobpattana, C Vaz, D Gundlach, ... IEEE Electron Device Letters 36 (1), 20-22, 2014 | 62 | 2014 |
| Insight into the output characteristics of III-V tunneling field effect transistors B Rajamohanan, D Mohata, A Ali, S Datta Applied Physics Letters 102 (9), 2013 | 58 | 2013 |
| Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for … R Pandey, H Madan, H Liu, V Chobpattana, M Barth, B Rajamohanan, ... 2015 Symposium on VLSI Technology (VLSI Technology), T206-T207, 2015 | 52 | 2015 |
| Tunnel transistors for energy efficient computing S Datta, R Bijesh, H Liu, D Mohata, V Narayanan 2013 IEEE International Reliability Physics Symposium (IRPS), 6A. 3.1-6A. 3.7, 2013 | 38 | 2013 |
| Tunnel transistors for low power logic S Datta, R Bijesh, H Liu, D Mohata, V Narayanan 2013 IEEE compound semiconductor integrated circuit symposium (CSICS), 1-4, 2013 | 34 | 2013 |
| Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs R Bijesh, DK Mohata, H Liu, S Datta 70th Device Research Conference, 203-204, 2012 | 30 | 2012 |
| Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor DK Mohata, R Bijesh, V Saripalli, T Mayer, S Datta 69th Device Research Conference, 203-204, 2011 | 26 | 2011 |
| Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors B Rajamohanan, D Mohata, Y Zhu, M Hudait, Z Jiang, M Hollander, ... Journal of Applied Physics 115 (4), 2014 | 25 | 2014 |
| Intrinsic reliability improvement in biaxially strained SiGe p-MOSFETs S Deora, A Paul, R Bijesh, J Huang, G Klimeck, G Bersuker, PD Krisch, ... IEEE electron device letters 32 (3), 255-257, 2011 | 25 | 2011 |
| Structural, morphological, and defect properties of metamorphic In0. 7Ga0. 3As/GaAs0. 35Sb0. 65 p-type tunnel field effect transistor structure grown by molecular beam epitaxy Y Zhu, MK Hudait, DK Mohata, B Rajamohanan, S Datta, D Lubyshev, ... Journal of Vacuum Science & Technology B 31 (4), 2013 | 12 | 2013 |
| Low-Temperature Atomic-Layer-Deposited High-κ Dielectric for p-Channel In0. 7Ga0. 3As/GaAs0. 35Sb0. 65 Heterojunction Tunneling Field-Effect Transistor B Rajamohanan, D Mohata, D Zhernokletov, B Brennan, RM Wallace, ... Applied Physics Express 6 (10), 101201, 2013 | 10 | 2013 |
| L. 2 Device Architecture, Material and Process Dependencies… 33 Date, S. Datta, A. Brand, J. Swenberg, S. Mahapatra K Joshi, S Hung, S Mukhopadhyay, V Chaudhary, N Nanaware, ... IEEE International Reliability Physics Symposium Proceedings C 4, 2.1, 2013 | 10 | 2013 |
| Scaled gate stacks for sub-20-nm CMOS logic applications through integration of thermal IL and ALD HfOx K Joshi, S Hung, S Mukhopadhyay, T Sato, M Bevan, B Rajamohanan, ... IEEE Electron Device Letters 34 (1), 3-5, 2012 | 10 | 2012 |
| Electron and hole photoemission detection for band offset determination of tunnel field-effect transistor heterojunctions W Li, Q Zhang, R Bijesh, OA Kirillov, Y Liang, I Levin, LM Peng, ... Applied Physics Letters 105 (21), 2014 | 9 | 2014 |
| Demonstration of p-type In R Pandey, H Madan, H Liu, V Chobpattana, M Barth, B Rajamohanan Proc. Symp. VLSI Technol, T206-T207, 0 | 8 | |
Dheeraj MohataSenior Integration Engineer, GCS IncVerified email at gcsincorp.com
