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Don Stark
Don Stark
Engineering Director, Google
Geverifieerd e-mailadres voor google.com
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A portable digital DLL for high-speed CMOS interface circuits
BW Garlepp, KS Donnelly, J Kim, PS Chau, JL Zerbe, C Huang, CV Tran, ...
IEEE Journal of solid-state circuits 34 (5), 632-644, 1999
3611999
Bus system optimization
JLV Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 6,643,787, 2003
3162003
Memory device supporting a dynamically configurable core organization
RE Perego, DC Stark, FA Ware
US Patent 6,889,304, 2005
2762005
Delay-locked loop circuitry for clock delay adjustment
KS Donnelly, PS Chau, MA Horowitz, TH Lee, MG Johnson, BC Lau, L Yu, ...
US Patent 6,125,157, 2000
2632000
Protocol for communication with dynamic memory
RM Barth, FA Ware, JB Dillon, DC Stark, CE Hampel, MM Griffin
US Patent 5,748,914, 1998
1811998
Delay locked loop circuitry for clock delay adjustment
KS Donnelly, PS Chau, MA Horowitz, TH Lee, MG Johnson, BC Lau, L Yu, ...
US Patent 6,539,072, 2003
1772003
Semiconductor memory with bypass circuit
T Furuyama, DC Stark
US Patent 5,479,370, 1995
1671995
Static control logic for microfluidic devices using pressure-gain valves
JA Weaver, J Melin, D Stark, SR Quake, MA Horowitz
Nature Physics 6 (3), 218-223, 2010
1642010
Power control system for synchronous memory device
EK Tsern, RM Barth, CE Hampel, DC Stark
US Patent 6,701,446, 2004
1522004
High performance cost optimized memory with delayed memory writes
RM Barth, FA Ware, DC Stark, CE Hampel, PG Davis, AM Abhyankar, ...
US Patent 6,075,730, 2000
1522000
Integrated circuit with timing adjustment mechanism and method
JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 6,950,956, 2005
1462005
Calibrated data communication system and method
JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 7,042,914, 2006
1452006
Single-clock, strobeless signaling system
DC Stark
US Patent 6,646,953, 2003
1402003
Memory device which receives write masking and automatic precharge information
FA Ware, CE Hampel, DC Stark, MM Griffin
US Patent 6,493,789, 2002
1402002
Memory device and system including a low power interface
EK Tsern, TJ Holman, RM Barth, AV Anderson, PG Davis, CE Hampel, ...
US Patent 6,378,018, 2002
1402002
A 660 MB/s interface megacell portable circuit in 0.3/spl mu/m-0.7/spl mu/m CMOS ASIC
KS Donnelly, YF Chan, JTC Ho, CV Tran, S Patel, B Lau, J Kim, PS Chau, ...
IEEE Journal of Solid-State Circuits 31 (12), 1995-2003, 1996
1401996
Semiconductor memory device which receives write masking information
FA Ware, CE Hampel, DC Stark, MM Griffin
US Patent 6,496,897, 2002
1392002
Memory module with offset data lines and bit line swizzle configuration
BW Garrett Jr, FA Ware, CE Hampel, RM Barth, D Stark, AM Abhyankar, ...
US Patent 6,839,266, 2005
1302005
Power control system for synchronous memory device
EK Tsern, RM Barth, CE Hampel, DC Stark
US Patent 6,263,448, 2001
1212001
High performance cost optimized memory
RM Barth, FA Ware, DC Stark, CE Hampel, PG Davis, AM Abhyankar, ...
US Patent 6,401,167, 2002
1172002
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