Andrea Bonetti
Andrea Bonetti
Verified email at csem.ch
TitleCited byYear
Polarbear: A 28-nm FD-SOI ASIC for decoding of polar codes
P Giard, A Balatsoukas-Stimming, TC Müller, A Bonetti, C Thibeault, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 7 (4 …, 2017
202017
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop
A Bonetti, A Teman, A Burg
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1850-1853, 2015
122015
Multipliers-driven perturbation of coefficients for low-power operation in reconfigurable FIR filters
A Bonetti, A Teman, P Flatresse, A Burg
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2388-2400, 2017
102017
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment
J Constantin, A Bonetti, A Teman, C Müller, L Schmid, A Burg
European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 261-264, 2016
102016
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder
P Meinerzhagen, A Bonetti, G Karakonstantis, C Roth, F Giirkaynak, ...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1426-1429, 2015
82015
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters
S Brenna, L Bettini, A Bonetti, A Bonfanti, AL Lacaita
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP …, 2015
62015
A tool for the assisted design of charge redistribution SAR ADCs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
62015
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
2014 37th International Convention on Information and Communication …, 2014
52014
An efficient tool for the assisted design of SAR ADCs capacitive DACs
S Brenna, A Bonetti, A Bonfanti, AL Lacaita
INTEGRATION, the VLSI journal 53, 88-99, 2016
42016
Voltage level shifter monitor with tunable voltage level shifter replica circuit
A Bonetti, JP Kulkarni, C Tokunaga, M Cho, PA Meinerzhagen, ...
US Patent App. 15/394,296, 2018
22018
Automated integration of dual-edge clocking for low-power operation in nanometer nodes
A Bonetti, N Preyss, A Teman, A Burg
ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (4), 62, 2017
22017
Low power and compact successive approximation ADC for bioelectronic chips
A BONETTI
Italy, 2012
22012
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
M Widmer, A Bonetti, A Burg
Proceedings of the 56th Annual Design Automation Conference 2019, 36, 2019
12019
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs
S Brenna, A Bonetti, AL Lacaita, A Bonfanti
2014 UKSim-AMSS 16th International Conference on Computer Modelling and …, 2014
12014
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices
BW Denkinger, F Ponzina, SS Basu, A Bonetti, S Balási, M Ruggiero, ...
IEEE Design & Test, 2019
2019
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space
EV Bravo, A Bonetti, A Burg
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
2019
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI
R Giterman, A Bonetti, A Burg, A Teman
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019
2019
Low-Power Design of Digital VLSI Circuits around the Point of First Failure
A Bonetti
EPFL, 2019
2019
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI
A Bonetti, J Constantin, A Ternan, A Burg
Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, 1-4, 2018
2018
Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors
A Bonetti, J Constantin, A Teman, A Burg
Nanotera Annual Meeting 2015, 2015
2015
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Articles 1–20