| Polarbear: A 28-nm FD-SOI ASIC for decoding of polar codes P Giard, A Balatsoukas-Stimming, TC Müller, A Bonetti, C Thibeault, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 7 (4 …, 2017 | 29 | 2017 |
| An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop A Bonetti, A Teman, A Burg 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1850-1853, 2015 | 16 | 2015 |
| DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment J Constantin, A Bonetti, A Teman, C Müller, L Schmid, A Burg European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 261-264, 2016 | 15 | 2016 |
| Multipliers-driven perturbation of coefficients for low-power operation in reconfigurable FIR filters A Bonetti, A Teman, P Flatresse, A Burg IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2388-2400, 2017 | 13 | 2017 |
| Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder P Meinerzhagen, A Bonetti, G Karakonstantis, C Roth, F Giirkaynak, ... 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1426-1429, 2015 | 8 | 2015 |
| A tool for the assisted design of charge redistribution SAR ADCs S Brenna, A Bonetti, A Bonfanti, AL Lacaita 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 7 | 2015 |
| FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems M Widmer, A Bonetti, A Burg 2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019 | 6 | 2019 |
| Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters S Brenna, L Bettini, A Bonetti, A Bonfanti, AL Lacaita 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP …, 2015 | 6 | 2015 |
| A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs S Brenna, A Bonetti, A Bonfanti, AL Lacaita 2014 37th International Convention on Information and Communication …, 2014 | 6 | 2014 |
| GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI R Giterman, A Bonetti, A Burg, A Teman IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 2042-2046, 2019 | 5 | 2019 |
| An efficient tool for the assisted design of SAR ADCs capacitive DACs S Brenna, A Bonetti, A Bonfanti, AL Lacaita Integration 53, 88-99, 2016 | 5 | 2016 |
| Automated integration of dual-edge clocking for low-power operation in nanometer nodes A Bonetti, N Preyss, A Teman, A Burg ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (4 …, 2017 | 4 | 2017 |
| Impact of memory voltage scaling on accuracy and resilience of deep learning based edge devices BW Denkinger, F Ponzina, SS Basu, A Bonetti, S Balási, M Ruggiero, ... IEEE Design & Test 37 (2), 84-92, 2019 | 3 | 2019 |
| Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space EV Bravo, A Bonetti, A Burg 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 3 | 2019 |
| Low power and compact successive approximation ADC for bioelectronic chips A BONETTI Italy, 2012 | 3 | 2012 |
| A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications J Narinx, R Giterman, A Bonetti, N Frigerio, C Aprile, A Burg, Y Leblebici 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 219-222, 2019 | 2 | 2019 |
| Voltage level shifter monitor with tunable voltage level shifter replica circuit A Bonetti, JP Kulkarni, C Tokunaga, M Cho, PA Meinerzhagen, ... US Patent App. 15/394,296, 2018 | 2 | 2018 |
| Gain-Cell Embedded DRAMs: Modeling and Design Space A Bonetti, R Golman, R Giterman, A Teman, A Burg IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 646-659, 2020 | 1 | 2020 |
| A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI A Bonetti, J Constantin, A Ternan, A Burg Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, 1-4, 2018 | 1 | 2018 |
| A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs S Brenna, A Bonetti, AL Lacaita, A Bonfanti 2014 UKSim-AMSS 16th International Conference on Computer Modelling and …, 2014 | 1 | 2014 |
Andreas BurgEPFL - Telecommunications Circuits LaboratoryVerified email at epfl.ch
