Denis Flandre
Denis Flandre
Verified email at uclouvain.be
Title
Cited by
Cited by
Year
A g/sub m//I/sub D/based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
F Silveira, D Flandre, PGA Jespers
IEEE journal of solid-state circuits 31 (9), 1314-1319, 1996
7031996
Substrate crosstalk reduction using SOI technology
JP Raskin, A Viviani, D Flandre, JP Colinge
IEEE Transactions on Electron Devices 44 (12), 2252-2261, 1997
3361997
Influence of device engineering on the analog and RF performances of SOI MOSFETs
V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ...
IEEE Transactions on Electron Devices 50 (3), 577-588, 2003
2072003
Modeling of ultrathin double-gate nMOS/SOI transistors
P Francis, A Terao, D Flandre, F Van de Wiele
IEEE Transactions on Electron Devices 41 (5), 715-720, 1994
1991994
Interests and limitations of technology scaling for subthreshold logic
D Bol, R Ambroise, D Flandre, JD Legat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (10 …, 2009
1772009
A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation
M Bawedin, S Cristoloveanu, D Flandre
IEEE Electron Device Letters 29 (7), 795-798, 2008
1712008
A formal study of power variability issues and side-channel attacks for nanoscale devices
M Renauld, FX Standaert, N Veyrat-Charvillon, D Kamel, D Flandre
Annual International Conference on the Theory and Applications of …, 2011
1512011
SleepWalker: A 25-MHz 0.4-V Sub- 7- Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ...
IEEE Journal of Solid-State Circuits 48 (1), 20-32, 2012
1382012
Design of SOI CMOS operational amplifiers for applications up to 300/spl deg/C
JP Eggermont, D De Ceuster, D Flandre, B Gentinne, PGA Jespers, ...
IEEE Journal of Solid-State Circuits 31 (2), 179-186, 1996
1311996
Comparison of TiSi2, CoSi2, and NiSi for thin‐film silicon‐on‐insulator applications
J Chen, JP Colinge, D Flandre, R Gillon, JP Raskin, D Vanhoenacker
Journal of The Electrochemical Society 144 (7), 2437, 1997
1301997
ULPFA: A new efficient design of a power-aware full adder
I Hassoune, D Flandre, I O'Connor, JD Legat
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 2066-2074, 2008
1212008
Analog performance and application of graded-channel fully depleted SOI MOSFETs
MA Pavanello, JA Martino, V Dessard, D Flandre
Solid-State Electronics 44 (7), 1219-1222, 2000
1192000
Micromachined thin-film sensors for SOI-CMOS co-integration
J Laconte, D Flandre, JP Raskin
Springer Science & Business Media, 2006
1172006
FinFET analogue characterization from DC to 110 GHz
D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ...
Solid-State Electronics 49 (9), 1488-1496, 2005
1162005
Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications
A Kranti, TM Chung, D Flandre, JP Raskin
Solid-State Electronics 48 (6), 947-959, 2004
1092004
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
MA Pavanello, JA Martino, D Flandre
Solid-State Electronics 44 (6), 917-922, 2000
1092000
Employing Si solar cell technology to increase efficiency of ultra‐thin Cu(In,Ga)Se2 solar cells
B Vermang, JT Wätjen, V Fjällström, F Rostvall, M Edoff, R Kotipalli, ...
Progress in Photovoltaics: Research and Applications 22 (10), 1023-1029, 2014
1082014
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
JP Raskin, TM Chung, V Kilchytska, D Lederer, D Flandre
IEEE Transactions on Electron Devices 53 (5), 1088-1095, 2006
1062006
Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
D Flandre, S Adriaensen, A Akheyar, A Crahay, L Demeûs, P Delatte, ...
Solid-State Electronics 45 (4), 541-549, 2001
1042001
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
D Flandre, A Viviani, JP Eggermont, B Gentinne, PGA Jespers
IEEE Journal of Solid-State Circuits 32 (7), 1006-1012, 1997
1021997
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