Hae-woong Yang
Title
Cited by
Cited by
Year
A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O transceiver in 65 nm CMOS
YH Song, R Bai, K Hu, HW Yang, PY Chiang, S Palermo
IEEE journal of solid-state circuits 48 (5), 1276-1289, 2013
552013
A reconfigurable 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65-nm CMOS
A Roshan-Zamir, O Elhadidy, HW Yang, S Palermo
IEEE Journal of Solid-State Circuits 52 (9), 2430-2447, 2017
432017
An 8–16 Gb/s, 0.65–1.05 pJ/b, voltage-mode transmitter with analog impedance modulation equalization and sub-3 ns power-state transitioning
YH Song, HW Yang, H Li, PY Chiang, S Palermo
IEEE Journal of Solid-State Circuits 49 (11), 2631-2643, 2014
232014
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS
EZ Tabasy
22*
A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS
O Elhadidy, A Roshan-Zamir, HW Yang, S Palermo
2015 Symposium on VLSI Circuits (VLSI Circuits), C224-C225, 2015
212015
A 6b 1.6 GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS
EZ Tabasy, A Shafik, S Huang, N Yang, S Hoyos, S Palermo
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
122012
A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR-and IIR-tap adaptation in 65-nm CMOS
A Roshan-Zamir, T Iwai, YH Fan, A Kumar, HW Yang, L Sledjeski, ...
IEEE Journal of Solid-State Circuits 54 (3), 672-684, 2018
102018
26.5 An 8-to-16Gb/s 0.65-to-1.05 pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS
YH Song, HW Yang, H Li, PY Chiang, S Palermo
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
92014
A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter
HW Yang, A Roshan-Zamir, YH Song, S Palermo
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 261-264, 2017
62017
10 Gb/s adaptive receive-side near-end and far-end crosstalk cancellation circuitry
B Min, NHW Yang, S Palermo
2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014
62014
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS
A Roshan-Zamir, T Iwai, YH Fan, A Kumar, HW Yang, L Sledjeski, ...
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018
52018
A 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65nm CMOS
A Roshan-Zamir, O Elhadidy, HW Yang, S Palermo
2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 1-4, 2016
52016
10 Gb/s adaptive receive-side merged near-end and far-end crosstalk cancellation circuitry in 65 nm CMOS
B Min, NHW Yang, S Palermo
Analog Integrated Circuits and Signal Processing 88 (2), 233-243, 2016
2016
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