Oskar Andersson
Title
Cited by
Cited by
Year
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing
J Constantin, A Dogan, O Andersson, P Meinerzhagen, JN Rodrigues, ...
VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International …, 2012
352012
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V T memory in 65nm CMOS
P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ...
ESSCIRC (ESSCIRC), 2012 Proceedings of the, 321-324, 2012
332012
A 290 mV Sub- ASIC for Real-Time Atrial Fibrillation Detection
O Andersson, KH Chon, L Sornmo, JN Rodrigues
IEEE, 2014
182014
Dual-V T 4kb sub-V T memories with< 1 pW/bit leakage in 65 nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues
ESSCIRC (ESSCIRC), 2013 Proceedings of the, 197-200, 2013
172013
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, A Burg, J Rodrigues
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016
122016
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, J Rodrigues
ESSCIRC, 2014
112014
Synthesis strategies for sub-V T systems
P Meinerzhagen, O Andersson, Y Sherazi, A Burg, J Rodrigues
Circuit Theory and Design (ECCTD), 2011 20th European Conference on, 552-555, 2011
102011
Improving Practical Sensitivity of Energy Optimized Wake-Up Receivers: Proof of Concept in 65-nm CMOS
NS Mazloum, JN Rodrigues, O Andersson, A Nejdel, O Edfors
IEEE Sensors Journal 16 (22), 8158-8166, 2016
92016
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI
B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1257-1268, 2018
72018
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3 V 7T sense-amplifierless SRAM in 28 nm FD-SOI
B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ...
European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 429-432, 2016
62016
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
J Constantin, A Dogan, O Andersson, P Meinerzhagen, J Rodrigues, ...
IFIP/IEEE International Conference on Very Large Scale Integration-System on …, 2012
42012
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography
S Asif, O Andersson, J Rodrigues, Y Kong
IET Computers & Digital Techniques 12 (2), 62-67, 2017
32017
Impact of switching activity on the energy minimum voltage for 65 nm sub-V T CMOS
O Andersson, SMY Sherazi, JN Rodrigues
NORCHIP, 2011, 1-4, 2011
32011
Ultra-low Voltage Embedded Memories–Design Aspects and a Biomedical Use-case
O Andersson
Department of Electrical and Information Technology, Lund University, 2016
22016
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
B Mohammadi, O Andersson, P Meinerzhagen, Y Sherazi, A Burg, ...
FTFC, 2014
22014
IR-drop reduction in sub-VT circuits by de-synchronization
A Karlsson, O Andersson, J Sparso, JN Rodrigues
Subthreshold Microelectronics Conference (SubVT), 2012 IEEE, 1-3, 2012
22012
An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI
B Mohammadi, O Andersson, X Luo, M Nouripayam, JN Rodrigues
Solid-State Circuits Conference (A-SSCC), 2016 IEEE Asian, 229-232, 2016
12016
Logic filter cache for wide-VDD-range processors
A Bardizbanyan, O Andersson, J Rodrigues, P Larsson-Edefors
Electronics, Circuits and Systems (ICECS), 2016 IEEE International …, 2016
2016
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS
O Andersson, JN Rodrigues
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2628-2631, 2015
2015
Reconfigurable and Selectively-Adaptive Signal Processing for Multi-Mode Wireless Communication
F Sheikh, O Andersson, CE Lee, F Xue, CH Chen, A Vaidya, A Sharma, ...
SiPS, 2015
2015
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Articles 1–20