Oskar Andersson
Oskar Andersson
Digital ASIC Designer, Oticon
Geverifieerd e-mailadres voor demant.com
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TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing
J Constantin, A Dogan, O Andersson, P Meinerzhagen, JN Rodrigues, ...
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chipá…, 2012
372012
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ...
2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012
342012
A 290 mV Sub- ASIC for Real-Time Atrial Fibrillation Detection
O Andersson, KH Chon, L Sornmo, JN Rodrigues
IEEE, 2014
192014
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues
2013 Proceedings of the ESSCIRC (ESSCIRC), 197-200, 2013
172013
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, A Burg, J Rodrigues
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016
142016
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
O Andersson, B Mohammadi, P Meinerzhagen, J Rodrigues
ESSCIRC, 2014
112014
Synthesis strategies for sub-VT systems
P Meinerzhagen, O Andersson, Y Sherazi, A Burg, J Rodrigues
2011 20th European Conference on Circuit Theory and Design (ECCTD), 552-555, 2011
102011
Improving Practical Sensitivity of Energy Optimized Wake-Up Receivers: Proof of Concept in 65-nm CMOS
NS Mazloum, JN Rodrigues, O Andersson, A Nejdel, O Edfors
IEEE Sensors Journal 16 (22), 8158-8166, 2016
92016
A 128 kb 7T SRAM using a single-cycle boosting mechanism in 28-nm FD–SOI
B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1257-1268, 2017
82017
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3 V 7T sense-amplifierless SRAM in 28 nm FD-SOI
B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ...
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 429-432, 2016
72016
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography
S Asif, O Andersson, J Rodrigues, Y Kong
IET Computers & Digital Techniques 12 (2), 62-67, 2017
42017
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
J Constantin, A Dogan, O Andersson, P Meinerzhagen, J Rodrigues, ...
IFIP/IEEE International Conference on Very Large Scale Integration-System oná…, 2012
42012
Impact of switching activity on the energy minimum voltage for 65 nm sub-VTCMOS
O Andersson, SMY Sherazi, JN Rodrigues
2011 NORCHIP, 1-4, 2011
32011
Ultra-low Voltage Embedded Memories–Design Aspects and a Biomedical Use-case
O Andersson
Department of Electrical and Information Technology, Lund University, 2016
22016
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
B Mohammadi, O Andersson, P Meinerzhagen, Y Sherazi, A Burg, ...
FTFC, 2014
22014
IR-drop reduction in sub-VT circuits by de-synchronization
A Karlsson, O Andersson, J Spars°, JN Rodrigues
2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3, 2012
22012
An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI
B Mohammadi, O Andersson, X Luo, M Nouripayam, JN Rodrigues
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 229-232, 2016
12016
A Wide-Operating Range Standard-Cell Based Memory in 28nm FD-SOI
O Andersson, B Mohammadi, JN Rodrigues
12016
Logic filter cache for wide-VDD-range processors
A Bardizbanyan, O Andersson, J Rodrigues, P Larsson-Edefors
2016 IEEE International Conference on Electronics, Circuits and Systemsá…, 2016
2016
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS
O Andersson, JN Rodrigues
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2628-2631, 2015
2015
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