Mottaqiallah Taouil
Mottaqiallah Taouil
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Memristor based computation-in-memory architecture for data-intensive applications
S Hamdioui, L Xie, HAD Nguyen, M Taouil, K Bertels, H Corporaal, H Jiao, ...
Proceedings of the 2015 design, automation & test in Europe conference …, 2015
992015
Test cost analysis for 3D die-to-wafer stacking
M Taouil, S Hamdioui, K Beenakker, EJ Marinissen
2010 19th IEEE Asian Test Symposium, 435-441, 2010
652010
Testing open defects in memristor-based memories
S Hamdioui, M Taouil, NZ Haron
IEEE Transactions on Computers 64 (1), 247-259, 2013
522013
Fast boolean logic mapped on memristor crossbar
L Xie, HA Du Nguyen, M Taouil, S Hamdioui, K Bertels
2015 33rd IEEE International Conference on Computer Design (ICCD), 335-342, 2015
512015
On maximizing the compound yield for 3D wafer-to-wafer stacked ICs
M Taouil, S Hamdioui, J Verbree, EJ Marinissen
2010 IEEE International Test Conference, 1-10, 2010
512010
Layer redundancy based yield improvement for 3D wafer-to-wafer stacked memories
M Taouil, S Hamdioui
2011 Sixteenth IEEE European Test Symposium, 45-50, 2011
312011
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
EJ Marinissen, B De Wachter, K Smith, J Kiesewetter, M Taouil, ...
2014 International Test Conference, 1-10, 2014
232014
Computation-in-memory based parallel adder
HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
222015
Test impact on the overall die-to-wafer 3D stacked IC cost
M Taouil, S Hamdioui, K Beenakker, EJ Marinissen
Journal of Electronic Testing 28 (1), 15-25, 2012
202012
Yield improvement and test cost optimization for 3D stacked ICs
S Hamdioui, M Taouil
2011 Asian Test Symposium, 480-485, 2011
202011
Scouting logic: A novel memristor-based logic design for resistive computing
L Xie, HA Du Nguyen, J Yu, A Kaichouhi, M Taouil, M AlFailakawi, ...
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 176-181, 2017
192017
Integral impact of BTI, PVT variation, and workload on SRAM sense amplifier
I Agbo, M Taouil, D Kraak, S Hamdioui, H Kükner, P Weckx, P Raghavan, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2017
192017
Using 3D-COSTAR for 2.5 D test cost optimization
M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik
2013 IEEE International 3D Systems Integration Conference (3DIC), 1-8, 2013
182013
A mapping methodology of boolean logic circuits on memristor crossbar
L Xie, HA Du Nguyen, M Taouil, S Hamdioui, K Bertels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
172017
Parallel matrix multiplication on memristor-based computation-in-memory architecture
A Haron, J Yu, R Nane, M Taouil, S Hamdioui, K Bertels
2016 International Conference on High Performance Computing & Simulation …, 2016
162016
Reconfigurable sparse/dense matrix-vector multiplier
G Kuzmanov, M Taouil
2009 International Conference on Field-Programmable Technology, 483-488, 2009
162009
Challenges and solutions in emerging memory testing
EI Vatajelu, P Prinetto, M Taouil, S Hamdioui
IEEE Transactions on Emerging Topics in Computing, 2017
152017
Interconnect networks for memristor crossbar
L Xie, HA Du Nguyen, M Taouil, S Hamdioui, K Bertels
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
152015
Yield improvement for 3D wafer-to-wafer stacked memories
M Taouil, S Hamdioui
Journal of Electronic Testing 28 (4), 523-534, 2012
152012
On the implementation of computation-in-memory parallel adder
HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017
142017
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