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Steve Groothuis
Steve Groothuis
Ayar Labs, Incorporated
Verified email at ayarlabs.com
Title
Cited by
Cited by
Year
Packaging effects on reliability of Cu/low-k interconnects
G Wang, C Merrill, JH Zhao, SK Groothuis, PS Ho
IEEE Transactions on Device and Materials Reliability 3 (4), 119-128, 2003
1552003
Chip-packaging interaction: a critical concern for Cu/low k packaging
G Wang, PS Ho, S Groothuis
Microelectronics Reliability 45 (7-8), 1079-1093, 2005
1342005
Shear stress evaluation of plastic packages
D Edwards, K Heinen, S Groothuis, J Martinez
IEEE Transactions on Components, Hybrids, and Manufacturing Technology 10 (4 …, 1987
1321987
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
SK Groothuis, J Li, H Zhang, PA Silvestri, X Li, S Luo, LG England, ...
US Patent 9,153,520, 2015
1052015
Computer aided stress modeling for optimizing plastic package reliability
S Groothuis, W Schroen, M Murtuza
23rd International Reliability Physics Symposium, 184-191, 1985
951985
Stress related failures causing open metallization
SK Groothuis, WH Schroen
25th International Reliability Physics Symposium, 1-8, 1987
691987
Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
J Li, SK Groothuis
US Patent App. 14/242,485, 2015
572015
Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
SS Vadhavkar, X Li, SK Groothuis, J Li, JS Gandhi, JM Derderian, ...
US Patent 9,691,746, 2017
44*2017
Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
SS Vadhavkar, X Li, SK Groothuis, J Li, JS Gandhi, JM Derderian, ...
US Patent 9,443,744, 2016
342016
3D simulation study of cell-cell interference in advanced NAND flash memory
H Liu, S Groothuis, C Mouli, J Li, K Parat, T Krishnamohan
2009 IEEE Workshop on Microelectronics and Electron Devices, 1-3, 2009
292009
Semiconductor die assembly and methods of forming thermal paths
J Li, SK Groothuis
US Patent 9,780,079, 2017
252017
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
J Li, SK Groothuis, M Koopmans
US Patent 9,287,240, 2016
242016
Semiconductor device assembly with vapor chamber
SK Groothuis, J Li
US Patent 10,215,500, 2019
232019
Numerical simulation of silicon wafer warpage due to thin film residual stresses
AH Abdelnaby, GP Potirniche, F Barlow, A Elshabini, S Groothuis, ...
2013 IEEE workshop on microelectronics and electron devices (WMED), 9-12, 2013
232013
Effect of packaging on interfacial cracking in Cu/low k damascene structures
G Wang, S Groothuis, PS Ho
53rd Electronic Components and Technology Conference, 2003. Proceedings …, 2003
222003
Semiconductor device packages with improved thermal management and related methods
S Groothuis, J Li, S Luo
US Patent 9,543,274, 2017
192017
Investigation of residual stress in wafer level interconnect structures induced by wafer processing
G Wanga, D Gan, S Groothuis, PS Ho
56th Electronic Components and Technology Conference 2006, 6 pp., 2006
182006
Parametric investigation of dynamic behavior of FBGA solder joints in board-level drop simulation
S Groothuis, C Chen, R Kovacevic
Proceedings Electronic Components and Technology, 2005. ECTC'05., 499-503, 2005
152005
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
J Li, SK Groothuis, M Koopmans
US Patent 9,818,625, 2017
142017
Semiconductor device packages including thermally insulating materials and methods of making and using such semiconductor packages
S Groothuis, J Li, S Luo
US Patent 8,816,494, 2014
142014
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