Kris Tiri
Kris Tiri
Qualcomm
Verified email at ee.ucla.edu
Title
Cited by
Cited by
Year
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
K Tiri, I Verbauwhede
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
8982004
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
K Tiri, M Akmal, I Verbauwhede
Proceedings of the 28th European solid-state circuits conference, 403-406, 2002
7282002
Securing encryption algorithms against DPA at the logic level: Next generation smart card technology
K Tiri, I Verbauwhede
International Workshop on Cryptographic Hardware and Embedded Systems, 125-136, 2003
2492003
A digital design flow for secure integrated circuits
K Tiri, I Verbauwhede
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1952006
Prototype IC with WDDL and differential routing–DPA resistance assessment
K Tiri, D Hwang, A Hodjat, BC Lai, S Yang, P Schaumont, I Verbauwhede
International Workshop on Cryptographic Hardware and Embedded Systems, 354-365, 2005
1852005
AES-based security coprocessor IC in 0.18-$ muhbox m $ CMOS with resistance to differential power analysis side-channel attacks
DD Hwang, K Tiri, A Hodjat, BC Lai, S Yang, P Schaumont, ...
IEEE Journal of Solid-State Circuits 41 (4), 781-792, 2006
1832006
Place and route for secure standard cell design
K Tiri, I Verbauwhede
Smart Card Research and Advanced Applications VI, 143-158, 2004
1512004
A VLSI design flow for secure side-channel attack resistant ICs
K Tiri, I Verbauwhede
Design, Automation and Test in Europe, 58-63, 2005
1252005
Securing embedded systems
DD Hwang, P Schaumont, K Tiri, I Verbauwhede
IEEE Computer Architecture Letters 4 (02), 40-49, 2006
1222006
Masking and dual-rail logic don’t add up
P Schaumont, K Tiri
International Workshop on Cryptographic Hardware and Embedded Systems, 95-106, 2007
1162007
A side-channel leakage free coprocessor IC in 0.18 µm CMOS for Embedded AES-based Cryptographic and Biometric Processing
K Tiri, D Hwang, A Hodjat, B Lai, S Yang, P Schaumont, I Verbauwhede
Proceedings of the 42nd annual Design Automation Conference, 222-227, 2005
1002005
Simulation models for side-channel information leaks
K Tiri, I Verbauwhecle
Proceedings. 42nd Design Automation Conference, 2005., 228-233, 2005
882005
Design method for constant power consumption of differential logic circuits
K Tiri, I Verbauwhede
Design, Automation and Test in Europe, 628-633, 2005
852005
A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-μm CMOS Technology
A Hodjat, DD Hwang, B Lai, K Tiri, I Verbauwhede
Proceedings of the 15th ACM Great Lakes symposium on VLSI, 60-63, 2005
812005
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]
K Tiri, I Verbauwhede
Proceedings of the 30th European Solid-State Circuits Conference, 179-182, 2004
752004
An analytical model for time-driven cache attacks
K Tiri, O Acıiçmez, M Neve, F Andersen
International Workshop on Fast Software Encryption, 399-413, 2007
702007
Side-channel attack pitfalls
K Tiri
2007 44th ACM/IEEE Design Automation Conference, 15-20, 2007
672007
Changing the odds against masked logic
K Tiri, P Schaumont
International Workshop on Selected Areas in Cryptography, 134-146, 2006
582006
Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis
IM Verbauwhede, KJV Tiri
US Patent 7,417,468, 2008
542008
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate
M Badaroglu, G Van der Plas, P Wambacq, L Balasubramanian, K Tiri, ...
IEEE journal of solid-state circuits 39 (7), 1119-1130, 2004
502004
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