Kunal Korgaonkar - Postdoc (Technion, Israel)
Kunal Korgaonkar - Postdoc (Technion, Israel)
PhD (UC San Diego, CA, USA), MS (IIT Madras, Chennai, India)
Geverifieerd e-mailadres voor ucsd.edu - Homepage
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The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency
A Gautham, K Korgaonkar, P Slpsk, S Balachandran, K Veezhinathan
Presented as part of the 2012 Workshop on Power-Aware Computing and Systems, 2012
302012
Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache
K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
162018
Smart Communications for Power Consumption Information
A Ambati, KK Korgaonkar, M Madhavan, RV Polavarapu
US Patent App. 13/213,254, 2013
92013
Incremental preparation of videos for delivery
M Chetlur, U Devi, S Kalyanaraman, R Kokku, K Korgaonkar
US Patent 9,152,220, 2015
82015
Characterization of User’s Behavior Variations for Design of Replayable Mobile Workloads
S Patil, Y Kim, K Korgaonkar, I Awwal, TS Rosing
International Conference on Mobile Computing, Applications, and Services, 51-70, 2015
72015
Size-proportional signature sharing for transactional memory systems
K Korgaonkar, K Garimella, K Veezhinathan
FASPP workshop, 2012
32012
Vorpal: Vector clock ordering for large persistent memory systems
K Korgaonkar, J Izraelevitz, J Zhao, S Swanson
Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing …, 2019
22019
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm
K Korgaonkar, R Ronen, A Chattopadhyay, S Kvatinsky
arXiv preprint arXiv:1910.10234, 2019
12019
Method and apparatus for reducing write congestion in non-volatile memory based last level caches
KK Korgaonkar, IS Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
US Patent App. 15/475,197, 2018
12018
To Cache Or To Bypass? A Fine Balance in The Emerging Memory Technology Era
K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
1
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein …
IS Bhati, H Liu, J Gaur, K Korgaonkar, S Manipatruni, S Subramoney, ...
US Patent 10,331,582, 2019
2019
Building Scalable Architectures Using Emerging Memory Technologies
KK Korgaonkar
UC San Diego, 2019
2019
Optimizing streaming of a group of videos
V Arya, M Chetlur, P Dutta, S Kalyanaraman, KK Korgaonkar, ...
US Patent 9,060,205, 2015
2015
Optimizing streaming of a group of videos
V Arya, M Chetlur, P Dutta, S Kalyanaraman, KK Korgaonkar, ...
US Patent 9,037,742, 2015
2015
Performance Evaluation: Of A Hardware Transactional Memory System
P Jain, K Korgaonkar
LAP Lambert Academic Publishing, 2012
2012
Reconstructing hardware transactional memory for workload optimized systems
K Korgaonkar, P Jain, D Tomar, K Garimella, V Kamakoti
International Workshop on Advanced Parallel Processing Technologies, 1-15, 2011
2011
Thread Synchronization: From Mutual Exclusion to Transactional Memory
V Kamakoti, K Korgaonkar
IETE Technical Review 28 (4), 302-315, 2011
2011
The Bitlet Model
K Korgaonkar, R Ronen, A Chattopadhyay, S Kvatinsky
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Artikelen 1–18