Hormoz Djahanshahi
Hormoz Djahanshahi
Senior Technical Staff Engineer, Microchip Technology
Verified email at microchip.com
Title
Cited by
Cited by
Year
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications
H Djahanshahi, CAT Salama
IEEE Journal of Solid-State Circuits 35 (6), 847-855, 2000
742000
On the design of mm-wave self-mixing-VCO architecture for high tuning-range and low phase noise
AHM Shirazi, A Nikpaik, R Molavi, S Lightbody, H Djahanshahi, ...
IEEE Journal of Solid-State Circuits 51 (5), 1210-1222, 2016
472016
A 20-GHz InP-HBT voltage-controlled oscillator with wide frequency tuning range
H Djahanshahi, N Saniei, SP Voinigescu, MC Malikpaard, CAT Salama
IEEE Transactions on Microwave Theory and Techniques 49 (9), 1566-1572, 2001
372001
25 GHz inductorless VCO in a 45 GHz SiGe technology
N Saniei, H Djahanshahi, CAT Salama
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 269-272, 2003
262003
Quantization noise improvement in a hybrid distributed-neuron ANN architecture
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
232001
A fully integrated tri-band, MIMO transceiver RFIC for 802.16 e
F Beaudoin, T Zortea, G Deliyannides, M Hiebert, M McAdam, M Venditti, ...
2008 IEEE Radio Frequency Integrated Circuits Symposium, 113-116, 2008
192008
Modeling and characterization of VCOs with MOS varactors for RF transceivers
P Sameni, C Siu, S Mirabbasi, H Djahanshahi, M Hamour, K Iniewski, ...
EURASIP Journal on Wireless Communications and Networking 2006, 1-12, 2006
172006
Gigabit-per-second, ECL-compatible I/O interface in 0.35-/spl mu/m CMOS
H Djahanshahi, F Hansen, CAT Salama
IEEE Journal of Solid-State Circuits 34 (8), 1074-1083, 1999
171999
A unified synapse-neuron building block for hybrid VLSI neural networks
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
171996
Sensitivity study and improvements on a nonlinear resistive-type neuron circuit
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
IEE Proceedings-Circuits, Devices and Systems 147 (4), 237-242, 2000
152000
Robust two-stage current-controlled oscillator in submicrometre CMOS
H Djahanshahi, CAT Salama
Electronics Letters 35 (21), 1837-1839, 1999
141999
A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
Proceedings of International Conference on Neural Networks (ICNN'96) 2, 868-873, 1996
131996
Low-noise flexible frequency clock generation from two fixed-frequency references
WM Lye, H Djahanshahi, M Hiebert, R Zavari
US Patent 9,112,517, 2015
122015
Electro-mechanical oscillator and method for generating a signal
H Djahanshahi, ST Lim
US Patent 9,071,194, 2015
122015
Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO
P Sameni, C Siu, K Iniewski, M Hamour, S Mirabbasi, H Djahanshahi, ...
2005 IEEE international symposium on circuits and systems, 5071-5074, 2005
122005
A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS
R Molavi, S Mirabbasi, H Djahanshahi
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1141-1144, 2011
112011
Variable-length digitally-controlled delay chain with interpolation-based tuning
JF Delage, H Djahanshahi, G Fortin
US Patent 7,884,660, 2011
112011
A robust hybrid neural architecture for an industrial sensor application
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits …, 1998
111998
Design and VLSI implementation of a unified synapse-neuron architecture
H Djahanshahi, M Ahmadi, GA Jullien, WC Miller
Proceedings of the Sixth Great Lakes Symposium on VLSI, 228-233, 1996
111996
A high speed SiGe VCO based on self injection locking scheme
N Saniei, H JAHANSHAHI
IRANIAN JOURNAL OF SCIENCE AND TECHNOLOGY TRANSACTION B-ENGINEERING 31 (6 …, 2007
102007
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Articles 1–20