Analysis & prognosis of sustainable development goals using big data-based approach during COVID-19 pandemic M Chopra, SK Singh, A Gupta, K Aggarwal, BB Gupta, F Colace
Sustainable Technology and Entrepreneurship 1 (2), 100012, 2022
136 2022 Highly scaled ruthenium interconnects S Dutta, S Kundu, A Gupta, G Jamieson, JFG Granados, J Bömmels, ...
IEEE Electron Device Letters 38 (7), 949-951, 2017
83 2017 Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ...
2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019
64 2019 High-aspect-ratio ruthenium lines for buried power rail A Gupta, S Kundu, L Teugels, J Bommels, C Adelmann, N Heylen, ...
2018 IEEE International Interconnect Technology Conference (IITC), 4-6, 2018
61 2018 Sub-100 nm2 Cobalt Interconnects S Dutta, S Beyne, A Gupta, S Kundu, S Van Elshocht, H Bender, ...
IEEE Electron Device Letters 39 (5), 731-734, 2018
57 2018 Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ...
2019 Symposium on VLSI Technology, T204-T205, 2019
44 2019 RC Benefits of Advanced Metallization OptionsI Ciofi, PJ Roussel, R Baert, A Contino, A Gupta, K Croes, CJ Wilson, ...
IEEE transactions on electron devices 66 (5), 2339-2345, 2019
42 2019 Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery J Ryckaert, A Gupta, A Jourdain, B Chava, G Van der Plas, D Verkest, ...
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 50-52, 2019
42 2019 Predicting catastrophic events using machine learning models for natural language processing M Chopra, SK Singh, K Aggarwal, A Gupta
Data mining approaches for big data and sentiment analysis in social media …, 2022
35 2022 SRAM with buried power distribution to improve write margin and performance in advanced technology nodes SM Salahuddin, KA Shaik, A Gupta, B Chava, M Gupta, P Weckx, ...
IEEE electron device letters 40 (8), 1261-1264, 2019
34 2019 Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ...
IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020
32 2020 Magnonic Band Structure in Vertical Meander-Shaped Thin Films G Gubbiotti, A Sadovnikov, E Beginin, S Nikitov, D Wan, A Gupta, ...
Physical Review Applied 15 (1), 014061, 2021
29 2021 Canadian Cardiovascular Society. The use of antiplatelet therapy in the outpatient setting: Canadian Cardiovascular Society guidelines AD Bell, A Roussin, R Cartier, WS Chan, JD Douketis, A Gupta, ME Kraw, ...
Can J Cardiol 27 (Suppl A), S1-59, 2011
27 2011 An analytical model of GaAs OPFET P Chakrabarti, A Gupta, NA Khan
Solid-State Electronics 39 (10), 1481-1490, 1996
27 1996 Characterization of sintered inkjet‐printed silicon nanoparticle thin films for thermoelectric devices E Drahi, A Gupta, S Blayac, S Saunier, P Benaben
physica status solidi (a) 211 (6), 1301-1307, 2014
21 2014 Alternative metals: from ab initio screening to calibrated narrow line models C Adelmann, K Sankaran, S Dutta, A Gupta, S Kundu, G Jamieson, ...
2018 IEEE International Interconnect Technology Conference (IITC), 154-156, 2018
20 2018 Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck Z Tőkei, V Vega, G Murdoch, M O’Toole, K Croes, R Baert, ...
2020 IEEE International Electron Devices Meeting (IEDM), 32.2. 1-32.2. 4, 2020
19 2020 Numerical simulation of an ion-implanted GaAs OPFET P Chakrabarti, M Madheswaran, A Gupta, NA Khan
IEEE transactions on Microwave Theory and Techniques 46 (10), 1360-1366, 1998
19 1998 PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
17 2022 Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
16 2020