| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 55 (12), 3349-3361, 2020 | 77 | 2020 |
| 17.5 A 12.5 GHz fractional-N type-I sampling PLL achieving 58fs integrated jitter M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 274-276, 2020 | 68 | 2020 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 14 | 2021 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 13 | 2021 |
| 32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations G Bè, A Parisi, L Bertulessi, L Ricci, L Scaletti, M Mercandelli, AL Lacaita, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (9), 3645-3649, 2022 | 4 | 2022 |
| A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters L Scaletti, G Bè, A Parisi, L Bertulessi, L Ricci, M Mercandelli, S Levantino, ... 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 20-24, 2022 | 1 | 2022 |
| Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators A Parisi, F Tesolin, M Mercandelli, L Bertulessi, AL Lacaita IEEE Microwave and Wireless Components Letters 31 (9), 1075-1078, 2021 | 1 | 2021 |
| Digitally assisted frequency synthesizers and data converters for wide-band radio systems A Parisi Politecnico di Milano, 2022 | | 2022 |
| Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits L Scaletti, A Parisi, L Bertulessi SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021 | | 2021 |
| A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity A Parisi, M Mercandelli, C Samori, AL Lacaita 2021 28th IEEE International Conference on Electronics, Circuits, and …, 2021 | | 2021 |
| High efficiency, low noise class-C LC-tuned CMOS VCO design in 28nm FDSOI technology A PARISI Politecnico di Milano, 2018 | | 2018 |
Luca BertulessiPolitecnico di MilanoVerified email at polimi.it
