| A scheme to design concurrent error detection techniques for the fast Fourier transform implemented in SRAM-based FPGAs R Gonzalez-Toral, P Reviriego, JA Maestro, Z Gao IEEE Transactions on Computers 67 (7), 1039-1045, 2018 | 17 | 2018 |
| Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection R González-Toral, S Liu, P Reviriego, JA Maestro IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1293-1302, 2018 | 5 | 2018 |
| A novel concurrent error detection technique for the fast fourier transform implemented in SRAM-based FPGAs R Gonzalez-Toral, P Reviriego, JA Maestro, Z Gao 2016 16th European Conference on Radiation and Its Effects on Components and …, 2016 | 2 | 2016 |
| A Fast Technique to Reduce Power Consumption on Linear Block Codes Used to Protect Registers R González-Toral, P Reviriego, JA Maestro, C Argyrides IEEE Transactions on Device and Materials Reliability 18 (2), 189-196, 2018 | 1 | 2018 |
Pedro ReviriegoUniversidad Politécnica de MadridGeverifieerd e-mailadres voor upm.es
