| A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency HP Le, M Seeman, SR Sanders, V Sathe, S Naffziger, E Alon 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 210-211, 2010 | 237 | 2010 |
| Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing VT Lee, A Alaghi, JP Hayes, V Sathe, L Ceze Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 13-18, 2017 | 152 | 2017 |
| Energy-efficient GHz-class charge-recovery logic VS Sathe, JY Chueh, MC Papaefthymiou Ieee journal of solid-state circuits 42 (1), 38-47, 2006 | 105 | 2006 |
| Resonant-clock design for a power-efficient, high-volume x86-64 microprocessor VS Sathe, S Arekapudi, A Ishii, C Ouyang, MC Papaefthymiou, S Naffziger IEEE Journal of Solid-State Circuits 48 (1), 140-149, 2012 | 90 | 2012 |
| Resonant-clock latch-based design VS Sathe, JC Kao, MC Papaefthymiou IEEE Journal of Solid-State Circuits 43 (4), 864-873, 2008 | 70 | 2008 |
| MATIC: Learning around errors for efficient low-voltage neural network accelerators S Kim, P Howe, T Moreau, A Alaghi, L Ceze, V Sathe 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2018 | 62 | 2018 |
| Clock stretcher for voltage droop mitigation V Sathe, S Naffziger, S Pant US Patent App. 13/013,013, 2012 | 58 | 2012 |
| Energy-efficient neural network acceleration in the presence of bit-level memory errors S Kim, P Howe, T Moreau, A Alaghi, L Ceze, VS Sathe IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4285-4298, 2018 | 53 | 2018 |
| A single-chip bidirectional neural interface with high-voltage stimulation and adaptive artifact cancellation in standard CMOS JP Uehlin, WA Smith, VR Pamula, EP Pepin, S Perlmutter, V Sathe, ... IEEE Journal of Solid-State Circuits 55 (7), 1749-1761, 2020 | 48 | 2020 |
| 187 MHz subthreshold-supply charge-recovery FIR WH Ma, JC Kao, VS Sathe, MC Papaefthymiou IEEE Journal of Solid-State Circuits 45 (4), 793-803, 2010 | 45 | 2010 |
| A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression WA Smith, JP Uehlin, SI Perlmutter, JC Rudell, VS Sathe 2017 Symposium on VLSI Circuits, C172-C173, 2017 | 41 | 2017 |
| A 0.0023 mm/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression JP Uehlin, WA Smith, VR Pamula, SI Perlmutter, JC Rudell, VS Sathe IEEE transactions on biomedical circuits and systems 14 (2), 319-331, 2019 | 39 | 2019 |
| Clock distribution network architecture with clock skew management JY Chueh, J Kao, V Sathe, MC Papaefthymiou, C Ziesler US Patent 7,956,664, 2011 | 39 | 2011 |
| Architecture considerations for stochastic computing accelerators VT Lee, A Alaghi, R Pamula, VS Sathe, L Ceze, M Oskin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 37 | 2018 |
| A 225 MHz resonant clocked ASIC chip CH Ziesler, J Kim, VS Sathe, MC Papaefthymiou Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 37 | 2003 |
| Clock distribution network architecture with resonant clock gating JY Chueh, J Kao, V Sathe, MC Papaefthymiou US Patent 7,719,317, 2010 | 34 | 2010 |
| Bandwidth extension on raw audio via generative adversarial networks S Kim, V Sathe arXiv preprint arXiv:1903.09027, 2019 | 32 | 2019 |
| Clock distribution network architecture for resonant-clocked systems JY Chueh, J Kao, V Sathe, MC Papaefthymiou US Patent 7,719,316, 2010 | 32 | 2010 |
| 14.5 A 0.6-to-1.1 V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS X Sun, A Boora, W Zhang, VR Pamula, V Sathe 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 230-232, 2019 | 30 | 2019 |
| An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS VR Pamula, X Sun, S Kim, F ur Rahman, B Zhang, VS Sathe 2018 IEEE Symposium on VLSI Circuits, 1-2, 2018 | 30 | 2018 |
Venkata Rajesh PamulaUniversity of Washington SeattleVerified email at uw.edu
