| Optimizing random test constraints using machine learning algorithms S Sokorac Proceedings of the design and verification conference and exhibition US (DVCon), 2017 | 19 | 2017 |
| Compute substrate for Software 2.0 J Vasiljevic, L Bajic, D Capalija, S Sokorac, D Ignjatovic, L Bajic, ... IEEE micro 41 (2), 50-55, 2021 | 13 | 2021 |
| SystemVerilog Interface Classes–More Useful Than You Thought S Sokorac DVCon, USA, 2016 | 2 | 2016 |
| Seamless place and route for heterogenous network of processor cores J Vasiljevic, L Bajic, D Capalija, S Sokorac US Patent 11,960,885, 2024 | | 2024 |
| Pre-staged instruction registers for variable length instruction set machine MR Dooley, M Trajkovic, RS Lal, S Sokorac US Patent App. 18/098,068, 2023 | | 2023 |
| Pre-staged instruction registers for variable length instruction set machine MR Dooley, M Trajkovic, RS Lal, S Sokorac US Patent 11,599,358, 2023 | | 2023 |
| IBM's POWER10 Processor J Vasiljevic, L Bajic, D Capalija, S Sokorac, D Ignjatovic, L Bajic, ... IEEE MICRO 41 (2), 50-55, 2021 | | 2021 |
| Testing the Testbench S Sokorac | | |
