| Masking the energy behavior of DES encryption [smart cards] H Saputra, N Vijaykrishnan, M Kandemir, MJ Irwin, R Brooks, S Kim, ... 2003 Design, Automation and Test in Europe Conference and Exhibition, 84-89, 2003 | 118 | 2003 |
| Dynamic scheduling algorithm and its schedulability analysis for certifiable dual-criticality systems T Park, S Kim Proceedings of the ninth ACM international conference on Embedded software …, 2011 | 75 | 2011 |
| Power-aware partitioned cache architectures S Kim, N Vijaykrishnan, M Kandemir, A Sivasubramaniam, MJ Irwin, ... Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 69 | 2001 |
| Instruction scheduling for low power A Parikh, S Kim, M Kandemir, N Vijaykrishnan, MJ Irwin Journal of VLSI signal processing systems for signal, image and video …, 2004 | 66 | 2004 |
| Energy behavior of Java applications from the memory perspective N Vijaykrishnan, M Kandemir, S Kim, S Tomar, A Sivasubramaniam, ... Java (TM) Virtual Machine Research and Technology Symposium (JVM 01), 2001 | 62 | 2001 |
| Partitioned instruction cache architecture for energy efficiency S Kim, N Vijaykrishnan, M Kandemir, A Sivasubramaniam, MJ Irwin ACM Transactions on Embedded Computing Systems (TECS) 2 (2), 163-185, 2003 | 61 | 2003 |
| Floating-ECC: Dynamic repositioning of error correcting code bits for extending the lifetime of STT-RAM caches H Farbeh, H Kim, SG Miremadi, S Kim IEEE Transactions on Computers 65 (12), 3661-3675, 2016 | 59 | 2016 |
| Enhanced buffer management policy that utilises message properties for delay-tolerant networks K Shin, S Kim IET communications 5 (6), 753-759, 2011 | 54 | 2011 |
| Area-efficient error protection for caches S Kim Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 51 | 2006 |
| Residue cache: A low-energy low-area L2 cache architecture via compression and partial hits S Kim, J Lee, J Kim, S Hong Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 47 | 2011 |
| Data organization and retrieval on parallel air channels: Performance and energy issues J Juran, AR Hurson, N Vijaykrishnan, S Kim Wireless Networks 10, 183-195, 2004 | 45 | 2004 |
| Ternary cache: Three-valued MLC STT-RAM caches S Hong, J Lee, S Kim 2014 IEEE 32nd International Conference on Computer Design (ICCD), 83-89, 2014 | 39 | 2014 |
| Exploiting same tag bits to improve the reliability of the cache memories J Hong, J Kim, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 254-265, 2014 | 38* | 2014 |
| A low-cost mechanism exploiting narrow-width values for tolerating hard faults in ALU S Hong, S Kim IEEE transactions on computers 64 (9), 2433-2446, 2014 | 33* | 2014 |
| Reducing area overhead for error-protecting large L2/L3 caches S Kim IEEE Transactions on Computers 58 (3), 300-310, 2008 | 33 | 2008 |
| Partial row activation for low-power dram system Y Lee, H Kim, S Hong, S Kim 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 31 | 2017 |
| Traffic management strategy for delay-tolerant networks K Shin, K Kim, S Kim Journal of Network and Computer Applications 35 (6), 1762-1770, 2012 | 29 | 2012 |
| Skinflint DRAM system: Minimizing DRAM chip writes for low power Y Lee, S Kim, S Hong, J Lee 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 28 | 2013 |
| Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling T Mahmood, S Kim, S Hong 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 26 | 2013 |
| A framework for correction of multi-bit soft errors in L2 caches based on redundancy K Bhattacharya, N Ranganathan, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (2), 194-206, 2008 | 25 | 2008 |
