| On variable ordering of binary decision diagrams for the application of multi-level logic synthesis M Fujita, Y Matsunaga, T Kakuda Proceedings of the European Conference on Design Automation., 50-54, 1991 | 384 | 1991 |
| An efficient equivalence checker for combinational circuits Y Matsunaga Proceedings of the 33rd annual Design Automation Conference, 629-634, 1996 | 162 | 1996 |
| Variable ordering algorithms for ordered binary decision diagrams and their evaluation M Fujita, H Fujisawa, Y Matsunaga IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 130 | 1993 |
| Multi-level logic optimization using binary decision diagrams. Y Matsunaga, M Fujita ICCAD 89, 556-559, 1989 | 110 | 1989 |
| A hardware maze router with application to interactive rip-up and reroute K Suzuki, Y Matsunaga, M Tachibana, T Ohtsuki IEEE transactions on computer-aided design of integrated circuits and …, 1986 | 67 | 1986 |
| Boolean resubstitution with permissible functions and binary decision diagrams H Sato, Y Yasue, Y Matsunaga, M Fujita Proceedings of the 27th ACM/IEEE Design Automation Conference, 284-289, 1991 | 59 | 1991 |
| In‐orbit performance of avalanche photodiode as radiation detector on board the picosatellite Cute‐1.7+ APD II J Kataoka, T Toizumi, T Nakamori, Y Yatsu, Y Tsubuku, Y Kuramoto, ... Journal of Geophysical Research: Space Physics 115 (A5), 2010 | 52 | 2010 |
| An exact and efficient algorithms for disjunctive decomposition Y Matsunaga Proccedings of the Workshop on Synthesis And System Integration of Mixed …, 1998 | 51 | 1998 |
| MINT--An Exact Algorithm for Finding Minimum Test Set-- Y Matsunaga IEICE Transactions on Fundamentals of Electronics, Communications and …, 1993 | 51 | 1993 |
| On computing the transitive closure of a state transition relation Y Matsunaga, PC McGeer, RK Brayton Proceedings of the 30th international design automation conference, 260-265, 1993 | 47 | 1993 |
| Redesign and automatic error correction of combinational circuits M Fujita, T Kakuda, Y Matsunaga Logic and Architecture Synthesis: Proceedings of the IFIP TC10/WG10. 5 …, 1991 | 46 | 1991 |
| Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gates Y Matsunaga US Patent 5,490,268, 1996 | 33 | 1996 |
| Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs M Fujita, Y Matsunaga 1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991 | 33 | 1991 |
| Cell library development methodology for throughput enhancement of character projection equipment M Sugihara, T Takata, K Nakamura, R Inanami, H Hayashi, K Kishimoto, ... IEICE Transactions on Electronics 89 (3), 377-383, 2006 | 30 | 2006 |
| Method of expressing a logic circuit Y Matsunaga, M Fujita US Patent 5,461,574, 1995 | 28 | 1995 |
| Area minimization algorithm for parallel prefix adders under bitwise delay constraints T Matsunaga, Y Matsunaga Proceedings of the 17th ACM Great Lakes symposium on VLSI, 435-440, 2007 | 27 | 2007 |
| Multi-operand adder synthesis on FPGAs using generalized parallel counters T Matsunaga, S Kimura, Y Matsunaga 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 337-342, 2010 | 26 | 2010 |
| Multi-level logic optimization M Fujita, Y Matsunaga, M Ciesielski Logic synthesis and verification, 29-63, 2002 | 26 | 2002 |
| A fast state reduction algorithm for incompletely specified finite state machine H Higuchi, Y Matsunaga Proceedings of the 33rd Annual Design Automation Conference, 463-466, 1996 | 26 | 1996 |
| Technology mapping technique for throughput enhancement of character projection equipment M Sugihara, T Takata, K Nakamura, R Inanami, H Hayashi, K Kishimoto, ... Emerging Lithographic Technologies X 6151, 297-308, 2006 | 24 | 2006 |
