Follow
Vitali Sokhin
Vitali Sokhin
Verified email at il.ibm.com
Title
Cited by
Cited by
Year
Threadmill: A post-silicon exerciser for multi-threaded processors
A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv
Proceedings of the 48th Design Automation Conference, 860-865, 2011
512011
Hardware verification using acceleration platform
M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ...
US Patent 8,832,502, 2014
182014
Control flow error localization
O Friedler, W Kadry, A Nahir, V Sokhin
US Patent 9,251,045, 2016
152016
Architectural failure analysis
O Friedler, W Kadry, A Nahir, V Sokhin
US Patent 9,569,345, 2017
142017
Effective post-silicon failure localization using dynamic program slicing
O Friedler, W Kadry, A Morgenshtein, A Nahir, V Sokhin
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
112014
Method and apparatus for post-silicon testing
A Adir, E Bin, S Copty, A Koyfman, S Landa, A Nahir, V Sokhin, E Tsanko
US Patent 8,892,386, 2014
102014
Test generation using expected mode of the target hardware device
P Sung-Boem, A Nahir, V Sokhin, W Kadry, JS Park, A Cho
US Patent 9,626,267, 2017
82017
Validation of multiprocessor hardware component
P Sung-Boem, A Nahir, V Sokhin, W Kadry, JS Park, A Cho
US Patent 10,528,443, 2020
72020
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation
G Papadimitriou, D Gizopoulos, A Chatzidimitriou, T Kolan, A Koyfman, ...
2016 IEEE 34th International Conference on Computer Design (ICCD), 544-551, 2016
72016
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification
D Lee, T Kolan, A Morgenshtein, V Sokhin, R Morad, A Ziv, V Bertacco
Proceedings of the 53rd Annual Design Automation Conference, 24, 2016
62016
Improving post-silicon validation efficiency by using pre-generated data
W Kadry, A Koyfman, D Krestyashyn, S Landa, A Nahir, V Sokhin
Haifa Verification Conference, 166-181, 2013
62013
Testing address translation cache
H Mendelson, T Kolan, V Sokhin
US Patent 11,263,150, 2022
42022
Comparative study of test generation methods for simulation accelerators
W Kadry, D Krestyashyn, A Morgenshtein, A Nahir, V Sokhin, JS Park, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 321-324, 2015
32015
Post-silicon validation of the ibm power9 processor
T Kolan, H Mendelson, V Sokhin, K Reick, E Tsanko, G Wetli
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 999 …, 2020
22020
Verification of atomic memory operations
T Har'el Kolan, H Mendelson, V Sokhin
US Patent 10,496,449, 2019
22019
Post-Silicon Validation of the IBM POWER8 Processor
T Kolan, H Mendelson, A Nahir, V Sokhin
Post-Silicon Validation and Debug, 343-363, 2019
22019
Recoverable exceptions generation and handling for post-silicon validation
H Mendelson, V Sokhin, T Kolan, H Theiler, S Doron
US Patent 11,226,370, 2022
12022
Partial-results post-silicon hardware exerciser
T Kolan, A Lvovsky, H Mendelson, V Sokhin
US Patent 11,204,859, 2021
12021
Automatically introducing register dependencies to tests
H Mendelson, T Kolan, V Sokhin
US Patent 11,194,705, 2021
12021
Attribute driven memory allocation
S Doron, WS Ibraheem, H Theiler, V Sokhin, H Hadad
US Patent 10,282,232, 2019
12019
The system can't perform the operation now. Try again later.
Articles 1–20