Ashay Rane
Ashay Rane
Graduate Research Assistant, The University of Texas at Austin
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Raccoon: Closing digital side-channels through obfuscated execution
A Rane, C Lin, M Tiwari
24th {USENIX} Security Symposium ({USENIX} Security 15), 431-446, 2015
Vale: Verifying high-performance cryptographic assembly code
B Bond, C Hawblitzel, M Kapritsos, KRM Leino, JR Lorch, B Parno, ...
26th {USENIX} Security Symposium ({USENIX} Security 17), 917-934, 2017
Everest: Towards a verified, drop-in replacement of HTTPS
K Bhargavan, B Bond, A Delignat-Lavaud, C Fournet, C Hawblitzel, ...
2nd Summit on Advances in Programming Languages (SNAPL 2017), 2017
Secure, Precise, and Fast Floating-Point Operations on x86 Processors
A Rane, C Lin, M Tiwari
USENIX Security Symposium, 2016
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics
A Rane, J Browne
2012 21st International Conference on Parallel Architectures and Compilation …, 2012
Autoscope: Automatic suggestions for code optimizations using perfexpert
OA Sopeju, M Burtscher, A Rane, J Browne
Evaluation, 2011
Experiences in tuning performance of hybrid MPI/OpenMP applications on quad-core systems
A Rane, D Stanzione
Proc. of 10th LCI Int’l Conference on High-Performance Clustered Computing, 2009
MicroStache: a lightweight execution context for in-process safe region isolation
L Mogosanu, A Rane, N Dautenhahn
International Symposium on Research in Attacks, Intrusions, and Defenses …, 2018
Performance optimization of data structures using memory access characterization
A Rane, J Browne
2011 IEEE International Conference on Cluster Computing, 570-574, 2011
Enhancing performance optimization of multicore/multichip nodes with data structure metrics
A Rane, J Browne
ACM Transactions on Parallel Computing (TOPC) 1 (1), 1-20, 2014
Unification of Static and Dynamic Analyses to Enable Vectorization
A Rane, R Krishnaiyer, CJ Newburn, J Browne, L Fialho, Z Matveev
27th International Workshop on Languages and Compilers for Parallel Computing, 2014
Poster: determining code segments that can benefit from execution on GPUs
A Rane, S Sardeshpande, J Browne
Proceedings of the 2011 Companion on High Performance Computing Networking …, 2011
PerfExpert and MACPO: Which code segments should (not) be ported to MIC?
A Rane, J Browne, L Koesterke
TACC-Intel High Performance Computing Symposium, 2012
A systematic process for efficient execution on Intel's heterogeneous computation nodes
A Rane, J Browne, L Koesterke
Proceedings of the 1st Conference of the Extreme Science and Engineering …, 2012
A Study of the Hybrid Programming Paradigm on Multicore Architectures
A Rane
Arizona State University, 2009
Broad-based side-channel defenses for modern microprocessors
A Rane
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