Satrajit Chatterjee
Satrajit Chatterjee
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DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
A Mishchenko, S Chatterjee, R Brayton
2006 43rd ACM/IEEE Design Automation Conference, 532-535, 2006
4452006
Improvements to technology mapping for LUT-based FPGAs
A Mishchenko, S Chatterjee, RK Brayton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
1682007
Improvements to combinational equivalence checking
A Mishchenko, S Chatterjee, R Brayton, N Een
2006 IEEE/ACM International Conference on Computer Aided Design, 836-843, 2006
1602006
Combinational and sequential mapping with priority cuts
A Mishchenko, S Cho, S Chatterjee, R Brayton
2007 IEEE/ACM International Conference on Computer-Aided Design, 354-361, 2007
1582007
Reducing structural bias in technology mapping
S Chatterjee, A Mishchenko, RK Brayton, X Wang, T Kam
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1442006
FRAIGs: A unifying representation for logic synthesis and verification
A Mishchenko, S Chatterjee, R Jiang, RK Brayton
ERL Technical Report, 2005
1372005
Verifying deadlock-freedom of communication fabrics
A Gotmanov, S Chatterjee, M Kishinevsky
International Workshop on Verification, Model Checking, and Abstract …, 2011
532011
Boolean factoring and decomposition of logic networks
A Mishchenko, R Brayton, S Chatterjee
2008 IEEE/ACM International Conference on Computer-Aided Design, 38-44, 2008
492008
xMAS: Quick formal modeling of communication fabrics to enable verification
S Chatterjee, M Kishinevsky, UY Ogras
IEEE Design & Test of Computers 29 (3), 80-88, 2012
482012
Factor cuts
S Chatterjee, A Mishchenko, R Brayton
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
472006
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
S Chatterjee, M Kishinevsky
International Conference on Computer Aided Verification, 321-338, 2010
452010
Quick formal modeling of communication fabrics to enable verification
S Chatterjee, M Kishinevsky, UY Ogras
2010 IEEE International High Level Design Validation and Test Workshop …, 2010
402010
Integrating logic synthesis, technology mapping, and retiming
A Mishchenko, S Chatterjee, R Brayton
Proc. IWLS'05, 2006
322006
Technology mapping with Boolean matching, supergates and choices
A Mishchenko, S Chatterjee, R Brayton, X Wang, T Kam
262005
An integrated technology mapping environment
R Brayton, S Chatterjee, M Ciesielski, A Mishchenko
Proc. International Workshop on Logic and Synthesis, 383-390, 2005
252005
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
S Chatterjee, M Kishinevsky
Formal Methods in System Design 40 (2), 147-169, 2012
232012
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
S Chatterjee, M Kishinevsky
Formal Methods in System Design 40 (2), 147-169, 2012
232012
On resolution proofs for combinational equivalence
S Chatterjee, A Mishchenko, R Brayton, A Kuehlmann
Proceedings of the 44th annual Design Automation Conference, 600-605, 2007
192007
Efficient FPGA mapping using priority cuts
S Cho, S Chatterjee, A Mishchenko, R Brayton
Poster.) Proc. FPGA 7, 2007
152007
A new incremental placement algorithm and its application to congestion-aware divisor extraction
S Chatterjee, R Brayton
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
132004
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