| A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS T Karnik, D Kurian, P Aseron, R Dorrance, E Alpman, A Nicoara, R Popov, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2018 | 54 | 2018 |
| A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL … JS Park, S Subramanian, L Lampert, T Mladenov, I Klotchkov, D Kurian, ... ISSCC, 208-210, 2021 | 46 | 2021 |
| Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration IA Abrosimov, VG Atyunin, AR Deas, IV Klotchkov US Patent 7,278,069, 2007 | 43 | 2007 |
| Skew calibration means and a method of skew calibration AR Deas, IV Klotchkov, IA Abrossimov, VG Atyunin US Patent 6,820,234, 2004 | 41 | 2004 |
| A fully integrated cryo-CMOS SoC for state manipulation, readout, and high-speed gate pulsing of spin qubits J Park, S Subramanian, L Lampert, T Mladenov, I Klotchkov, DJ Kurian, ... IEEE Journal of Solid-State Circuits 56 (11), 3289-3306, 2021 | 35 | 2021 |
| Skew calibration means and a method of skew calibration IV Klotchkov US Patent 6,298,465, 2001 | 27 | 2001 |
| Towards synthesis of monotonic asynchronous circuits from signal transition graphs N Starodoubtsev, S Bystrov, M Goncharov, I Klotchkov, A Smirnov Proceedings Second International Conference on Application of Concurrency to …, 2001 | 19 | 2001 |
| 13.1 a fully integrated cryo-cmos soc for qubit control in quantum computers capable of state manipulation, readout and high-speed gate pulsing of spin qubits in intel 22nm ffl … JS Park, S Subramanian, L Lampert, T Mladenov, I Klotchkov, DJ Kurian, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 208-210, 2021 | 18 | 2021 |
| 2.4 a distributed autonomous and collaborative multi-robot system featuring a low-power robot soc in 22nm cmos for integrated battery-powered minibots V Honkote, D Kurian, S Muthukumar, D Ghosh, S Yada, K Jain, B Jackson, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 48-50, 2019 | 16 | 2019 |
| Power specification, simulation and verification of SystemC designs K Gagarski, M Petrov, M Moiseev, I Klotchkov 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | 12 | 2016 |
| A codesign case study: implementing arithmetic functions in FPGAs IV Klotchkov, S Pedersen Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based …, 1996 | 11 | 1996 |
| Design of a low power SoC testchip for wearables and IoTs M Wu, R Iyer, Y Hoskote, S Zhang, J Zamora, G Fabila, I Klotchkov, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-27, 2015 | 7 | 2015 |
| Data processing system I Abrosimov, I Klotchkov US Patent App. 10/066,775, 2002 | 6 | 2002 |
| SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC M Moiseev, R Popov, I Klotchkov Proceedings of DVCON Europe, 15, 2020 | 5 | 2020 |
| Synthesis of asynchronous interface circuits by STG refinement N Starodoubtsev, M Goncharov, I Klotchkov, A Smirnov Asynchronous Interfaces: Tools, Techniques, and Implementations, 65-74, 2000 | 5 | 2000 |
| Microphone array post-filter in frequency domain for speech recognition using short-time log-spectral amplitude estimator and spectral harmonic/noise classifier S Salishev, I Klotchkov, A Barabanov Speech and Computer: 19th International Conference, SPECOM 2017, Hatfield …, 2017 | 3 | 2017 |
| Static analysis method for deadlock detection in SystemC designs M Moiseev, A Zakharov, I Klotchkov, S Salishev 2011 International Symposium on System on Chip (SoC), 42-47, 2011 | 3 | 2011 |
| Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment MV Goncharov, AB Smirnov, IV Klotchkov, NA Starodoubtsev Proceedings 1998 International Conference on Application of Concurrency to …, 1998 | 3 | 1998 |
| STG refinement for synthesis of negative gates' circuits M Goncharov, I Klotchkov, E Klypkin, A Smirnov, N Starodoubtsev Handouts of the AciD-WG Workshop, Univ. of Newcastle upon Tyne, Tech. report …, 1999 | 2 | 1999 |
| Verification driven synthesis of asynchronous circuits from STG specification IV Krotchkov, AB Smirnov, NA Starodoubtsev Power and Timing Modeling, Optimization and Simulation (PATMOS), 377-386, 1998 | 2 | 1998 |
Alexander SmirnovBoston UniversityGeverifieerd e-mailadres voor siemens.com
