| Noise-Aware FET Circuit Design Based on C/ID-Invariant A Wahid, J Atkinson, R Bindiganavile, F Jazaeri, A Tajalli IEEE Transactions on Circuits and Systems II: Express Briefs 70 (7), 2330-2334, 2023 | 5 | 2023 |
| Power system emulator based on pll architecture A Wahid, SA Sadat, M Ardakani, A Tajalli 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020 | 4 | 2020 |
| Optimal PAM Order for Wireline Communication A Wahid, R Bindiganavile, A Tajalli 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 3 | 2021 |
| Digitally-assisted peak detector for periodic signal A Wahid, A Tajalli 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems …, 2020 | 3 | 2020 |
| A 59-fs-rms 35-GHz PLL with FoM of −241-dB in BiCMOS/SiGe Technology R Bindiganavile, A Wahid, J Atkinson, A Tajalli 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 163-166, 2022 | 1 | 2022 |
| Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication A Wahid, R Bindiganavile, A Tajalli 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | | 2024 |
| A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI R Bindiganavile, A Wahid, A Tajalli 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | | 2024 |
| Trade-Offs in Design of Low-Jitter and Wideband Phase-Locked Loops A WAHID, A Tajalli, R Bindiganavile Available at SSRN 4942040, 0 | | |
| Trade-Offs in Design of Low-Jitter and Wideband Phase-Locked Loops R Bindiganavile, A Wahid, A Tajalli Available at SSRN 4819329, 0 | | |
Armin TajalliUniversity of UtahVerified email at utah.edu
