Sanjay Pant
Sanjay Pant
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Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
RazorII: In situ error detection and correction for PVT and SER tolerance
S Das, C Tokunaga, S Pant, WH Ma, S Kalaiselvan, K Lai, DM Bull, ...
IEEE Journal of Solid-State Circuits 44 (1), 32-48, 2008
A self-tuning DVS processor using delay-error detection and correction
S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge
IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006
Razor II: In situ error detection and correction for PVT and SER tolerance
D Blaauw, S Kalaiselvan, K Lai, WH Ma, S Pant, C Tokunaga, S Das, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency
B Zhai, L Nazhandali, J Olson, A Reeves, M Minuth, R Helfand, S Pant, ...
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 154-155, 2006
Energy-efficient subthreshold processor design
B Zhai, S Pant, L Nazhandali, S Hanson, J Olson, A Reeves, M Minuth, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (8 …, 2009
Power grid physics and implications for CAD
S Pant, E Chiprout
Proceedings of the 43rd annual Design Automation Conference, 199-204, 2006
Energy optimization of subthreshold-voltage sensor network processors
L Nazhandali, B Zhai, A Olson, A Reeves, M Minuth, R Helfand, S Pant, ...
32nd International Symposium on Computer Architecture (ISCA'05), 197-207, 2005
AUDIT: Stress testing the automatic way
Y Kim, LK John, S Pant, S Manne, M Schulte, WL Bircher, MSS Govindan
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 212-223, 2012
5.6 adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor
A Grenat, S Pant, R Rachala, S Naffziger
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
Vectorless analysis of supply noise induced delay variation
S Pant, D Blaauw, V Zolotov, S Sundareswaran, R Panda
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
A stochastic approach to power grid analysis
S Pant, D Blaauw, V Zolotov, S Sundareswaran, R Panda
Proceedings of the 41st annual Design Automation Conference, 171-176, 2004
Clock stretcher for voltage droop mitigation
V Sathe, S Naffziger, S Pant
US Patent App. 13/013,013, 2012
Design and Analysis of Power Distribution Networks in VLSI Circuits.
S Pant
Steamroller module and adaptive clocking system in 28 nm CMOS
K Wilcox, R Cole, HR Fair III, K Gillespie, A Grenat, C Henrion, R Jotwani, ...
IEEE Journal of Solid-State Circuits 50 (1), 24-34, 2014
Electronic design automation for integrated circuits handbook-2 volume set
L Lavagno, RF Damiano, R Camposano, G Martin, L Scheffer, SP Khatri, ...
CRC press, 2006
Static timing analysis considering power supply variations
S Pant, D Blaauw
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
Patient positioning in shoulder arthroscopy: Which is best?
J Rojas, F Familiari, A Bitzer, U Srikumaran, R Papalia, EG McFarland
Joints 7 (02), 046-055, 2019
Guardband reduction for multi-core data processor
S Manne, R Desikan, S Pant, Y Kim
US Patent 9,223,383, 2015
Circuit techniques for suppression and measurement of on-chip inductive supply noise
S Pant, D Blaauw
ESSCIRC 2008-34th European Solid-State Circuits Conference, 134-137, 2008
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