| A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ... IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013 | 106 | 2013 |
| Formal verification of phase-locked loops using reachability analysis and continuization M Althoff, A Rajhans, BH Krogh, S Yaldiz, X Li, L Pileggi Communications of the ACM 56 (10), 97-104, 2013 | 105 | 2013 |
| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 59 | 2020 |
| An integral path self-calibration scheme for a dual-loop PLL M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, JA Tierno, ... IEEE Journal of Solid-State Circuits 48 (4), 996-1008, 2013 | 53 | 2013 |
| SRAM parametric failure analysis J Wang, S Yaldiz, X Li, LT Pileggi Proceedings of the 46th annual design automation conference, 496-501, 2009 | 51 | 2009 |
| Common-centroid layouts for analog circuits: Advantages and limitations AK Sharma, M Madhusudan, SM Burns, P Mukherjee, S Yaldiz, R Harjani, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 36 | 2021 |
| Indirect performance sensing for on-chip self-healing of analog and RF circuits S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ... IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2243-2252, 2014 | 34 | 2014 |
| Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ... Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 25 | 2013 |
| A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS JO Plouchart, MA Ferriss, AS Natarajan, A Valdes-Garcia, B Sadhu, ... IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2009-2017, 2013 | 24 | 2013 |
| Stochastic modeling and optimization for energy management in multicore systems: A video decoding case study S Yaldiz, A Demir, S Tasiran IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 17 | 2008 |
| A 21.8–27.5 GHz PLL in 32nm SOI using Gm linearization to achieve− 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier B Sadhu, MA Ferriss, JO Plouchart, AS Natarajan, AV Rylyakov, ... 2012 IEEE Radio Frequency Integrated Circuits Symposium, 75-78, 2012 | 15 | 2012 |
| Performance-aware common-centroid placement and routing of transistor arrays in analog circuits AK Sharma, M Madhusudan, SM Burns, S Yaldiz, P Mukherjee, R Harjani, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 14 | 2021 |
| A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology A Lotfy, SFS Farooq, QS Wang, S Yaldiz, P Mosalikanti, N Kurd 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 13 | 2015 |
| Indirect phase noise sensing for self-healing voltage controlled oscillators S Yaldiz, V Calayir, X Li, L Pileggi, AS Natarajan, MA Ferriss, J Tierno 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 13 | 2011 |
| Characterizing and exploiting task load variability and correlation for energy management in multi core systems S Yaldiz, A Demir, S Tasiran, P Ienne, Y Leblebici 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 135-140, 2005 | 13 | 2005 |
| An integral path self-calibration scheme for a 20.1–26.7 GHz dual-loop PLL in 32nm SOI CMOS M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, A Babakhani, ... 2012 Symposium on VLSI Circuits (VLSIC), 176-177, 2012 | 12 | 2012 |
| Efficient statistical analysis of read timing failures in SRAM circuits S Yaldiz, U Arslan, X Li, L Pileggi 2009 10th International Symposium on Quality Electronic Design, 617-621, 2009 | 12 | 2009 |
| The ALIGN open-source analog layout generator: V1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 8 | 2020 |
| PLL bandwidth correction with offset compensation MA Ferriss, A Natarajan, B Parker, A Rylyakov, JA Tierno, S Yaldiz US Patent 8,493,113, 2013 | 8 | 2013 |
| A digital LDO in 22nm CMOS with a 4b self-triggered binary search windowed flash ADC featuring automatic analog layout generator framework X Liu, S Yaldiz, P Mukherjee, S Burns, H Krishnamurthy, K Ravichandran, ... 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2-4, 2022 | 5 | 2022 |
